posedge_event for clock is not recognized with pos/neg edge

[zhuanhao-wu]

https://github.com/intel/systemc-compiler/blob/main/designs/tests/cthread/test_if.cpp

Notice that there is an always following the posedge_event:

SC_THREAD(if_stmt_wait0);
sensitive << clk.posedge_event();
async_reset_signal_is(arstn, false);


hSenslist if_stmt_wait0 [
  hSensvar NONAME [
    hBuiltinFunction posedge_event [
      hVarref clk_scclang_global_1 NOLIST
    ]
    hNoop always NOLIST
  ]
  hSensvar ASYNC [
    hVarref arstn_scclang_global_0 NOLIST
    hLiteral 0 NOLIST
  ]
]

Normally the clock will be specified as follows:

hSenslist if_stmt_wait0 [
  hSensvar NONAME [
    hVarref clk_scclang_global_1 NOLIST
    hBuiltinFunction pos NOLIST
  ]
  hSensvar ASYNC [
    hVarref arstn_scclang_global_0 NOLIST
    hLiteral 0 NOLIST
  ]
 
]