[VTA] [Chisel] fix tensor issue/commit in gemm #3637
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tmoreau89
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Jul 27, 2019
| @@ -39,10 +39,10 @@ class MAC(aBits: Int = 8, bBits: Int = 8, cBits: Int = 16) extends Module { | |||
| val rA = RegNext(io.a) | |||
| val rB = RegNext(io.b) | |||
| val rC = RegNext(io.c) | |||
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These edits will add noise to the github history of the file. Can we fix all of the spacing issues in a separate PR for the Chisel codebase until we have lint tests?
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Actually I just realized - the edit was adding a tab; the spacing issues were already fixed before. That said a lint test would have caught that
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Sure, let me try to do that.
Btw, all the ASF headers for the entire codebase has the same issue.
tmoreau89
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Jul 27, 2019
wweic
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Aug 9, 2019
* fix tensor issue/commit in gemm * remove trailing spaces
wweic
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Sep 6, 2019
* fix tensor issue/commit in gemm * remove trailing spaces
tqchen
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Mar 29, 2020
* fix tensor issue/commit in gemm * remove trailing spaces
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Background
The
inflightcounter tracks the number ofinpandwgttensors issue to theMatrixVectorMultiplicationmodule.Bug
The current bug is related to the way the counter is being incremented. The counter is incremented on the same state
sExewhere theGEMMunit asserts thedonesignal. Since the increment happen on the next cycle then the unit will assertdonebut the values are not written back to memory yet because of the depth of the pipeline.Solution
Now, we increment the
inflightcounter once we read the tensors and decrement it when we write-back.