[CODEGEN] Fix code generation bugs for C/CUDA & Improve VerifyGPUCode pass #6041
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| @@ -720,14 +720,15 @@ void CodeGenC::VisitStmt_(const StoreNode* op) { | |||
| } else { | |||
| CHECK(is_one(op->predicate)) << "Predicated store is not supported"; | |||
| arith::PVar<PrimExpr> base; | |||
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| // The assignment below introduces side-effect, and the resulting value cannot | |||
| // be reused across multiple expression, thus a new scope is needed | |||
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Great!
Do we need to add some UTs to cover these cases?
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tir.reinterpretIf we call
tir.reinterpreton an rvalue, the existing strategy will generate the wrong code. Because we cannot get the address of an rvalue. To fix this, we need to store the rvalue into a temporary variable and get the address of this temporary variable.This bug is the same as the bug in [CODEGEN] update codegen for vector operation #711. In the old PR, I only added a new SSA scope for the "else" branch. But in the "then" branch, it has the same problem. So I moved the addition of a new SSA scope to the top-level to cover both "then" and "else" branch.
Besides checking the LoadNode, we should also check the StoreNode.
cc @weberlo @tqchen @jcf94