H7: Tune SDRAM timings

Author: facchinm

libraries/Portenta_SDRAM/src/ram_internal.c

@@ -42,18 +42,19 @@ static HAL_StatusTypeDef FMC_SDRAM_Clock_Config(void)
   /* FMC Kernel Clock = PLL2_VCO Output/PLL_R = 800/4 = 200 Mhz */
   RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FMC;
   RCC_PeriphCLKInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_PLL2;
-  RCC_PeriphCLKInitStruct.PLL2.PLL2RGE = RCC_PLL1VCIRANGE_2;
 #ifdef ARDUINO_GIGA
-  RCC_PeriphCLKInitStruct.PLL2.PLL2M = 3;
-  RCC_PeriphCLKInitStruct.PLL2.PLL2N = 120;
+  RCC_PeriphCLKInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
+  RCC_PeriphCLKInitStruct.PLL2.PLL2M = 2;
+  RCC_PeriphCLKInitStruct.PLL2.PLL2N = 60;
 #else
+  RCC_PeriphCLKInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2;
   RCC_PeriphCLKInitStruct.PLL2.PLL2M = 5;
-  RCC_PeriphCLKInitStruct.PLL2.PLL2N = 160;
+  RCC_PeriphCLKInitStruct.PLL2.PLL2N = 95;
 #endif
   RCC_PeriphCLKInitStruct.PLL2.PLL2FRACN = 0;
   RCC_PeriphCLKInitStruct.PLL2.PLL2P = 2;
-  RCC_PeriphCLKInitStruct.PLL2.PLL2R = 4;
-  RCC_PeriphCLKInitStruct.PLL2.PLL2Q = 3;
+  RCC_PeriphCLKInitStruct.PLL2.PLL2Q = 2;
+  RCC_PeriphCLKInitStruct.PLL2.PLL2R = 2;
   RCC_PeriphCLKInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
   return HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);
 }