|
22 | 22 | };
|
23 | 23 | };
|
24 | 24 |
|
| 25 | +&pinctrl { |
| 26 | + sci7_default: sci7_default { |
| 27 | + group1 { |
| 28 | + /* tx rx */ |
| 29 | + psels = <RA_PSEL(RA_PSEL_SCI_7, 6, 13)>, |
| 30 | + <RA_PSEL(RA_PSEL_SCI_7, 6, 14)>, |
| 31 | + <RA_PSEL(RA_PSEL_SCI_7, 6, 11)>, |
| 32 | + <RA_PSEL(RA_PSEL_SCI_7, 4, 4)>; |
| 33 | + }; |
| 34 | + }; |
| 35 | + sci6_default: sci6_default { |
| 36 | + group1 { |
| 37 | + /* tx rx */ |
| 38 | + psels = <RA_PSEL(RA_PSEL_SCI_6, 5, 6)>, |
| 39 | + <RA_PSEL(RA_PSEL_SCI_6, 3, 4)>, |
| 40 | + <RA_PSEL(RA_PSEL_SCI_6, 5, 3)>, |
| 41 | + <RA_PSEL(RA_PSEL_SCI_6, 5, 2)>; |
| 42 | + }; |
| 43 | + }; |
| 44 | + |
| 45 | +}; |
| 46 | + |
| 47 | + |
| 48 | +&sci7 { |
| 49 | + pinctrl-0 = <&sci7_default>; |
| 50 | + pinctrl-names = "default"; |
| 51 | + status = "okay"; |
| 52 | + |
| 53 | + uart7: uart { |
| 54 | + status = "okay"; |
| 55 | + current-speed = <115200>; |
| 56 | + }; |
| 57 | +}; |
| 58 | + |
| 59 | +&sci6 { |
| 60 | + status = "okay"; |
| 61 | + pinctrl-0 = <&sci6_default>; |
| 62 | + pinctrl-names = "default"; |
| 63 | + |
| 64 | + uart6: uart { |
| 65 | + status = "okay"; |
| 66 | + current-speed = <115200>; |
| 67 | + }; |
| 68 | +}; |
| 69 | + |
| 70 | +&sci5 { |
| 71 | + status = "okay"; |
| 72 | + |
| 73 | + uart5: uart { |
| 74 | + status = "okay"; |
| 75 | + current-speed = <115200>; |
| 76 | + }; |
| 77 | +}; |
| 78 | + |
| 79 | + |
25 | 80 | / {
|
26 | 81 | zephyr,user {
|
27 | 82 | digital-pin-gpios = <&ioport1 5 GPIO_ACTIVE_HIGH>,
|
|
64 | 119 |
|
65 | 120 | <&ioport1 7 GPIO_ACTIVE_HIGH>, // LEDR
|
66 | 121 | <&ioport4 0 GPIO_ACTIVE_HIGH>,
|
67 |
| - <&ioport8 0 GPIO_ACTIVE_HIGH>; |
| 122 | + <&ioport8 0 GPIO_ACTIVE_HIGH>, |
| 123 | + |
| 124 | + // I2C pins |
| 125 | + <&ioport5 11 GPIO_ACTIVE_HIGH>, /* D37 | SDA1 */ |
| 126 | + <&ioport5 12 GPIO_ACTIVE_HIGH>, /* D38 | SCL1 */ |
| 127 | + <&ioport3 2 GPIO_ACTIVE_HIGH>, /* D39 | SDA2 */ |
| 128 | + <&ioport3 1 GPIO_ACTIVE_HIGH>, /* D40 | SCL2 */ |
| 129 | + |
| 130 | + // CAN pins |
| 131 | + <&ioport2 2 GPIO_ACTIVE_HIGH>, /* D41 | CAN RX */ |
| 132 | + <&ioport2 3 GPIO_ACTIVE_HIGH>, /* D42 | CAN TX */ |
| 133 | + <&ioport6 10 GPIO_ACTIVE_HIGH>, /* D43 | CAN1 RX */ |
| 134 | + <&ioport6 9 GPIO_ACTIVE_HIGH>, /* D44 | CAN1 TX */ |
| 135 | + |
| 136 | + // SPI pins |
| 137 | + <&ioport1 0 GPIO_ACTIVE_HIGH>, /* D45 | MISO1 */ |
| 138 | + <&ioport1 1 GPIO_ACTIVE_HIGH>, /* D46 | MOSI1 */ |
| 139 | + <&ioport1 2 GPIO_ACTIVE_HIGH>, /* D47 | SCLK1 */ |
| 140 | + <&ioport1 3 GPIO_ACTIVE_HIGH>, /* D48 | CS1 */ |
| 141 | + |
| 142 | + // UART pins |
| 143 | + <&ioport6 13 GPIO_ACTIVE_HIGH>, /* D49 | TX2 */ |
| 144 | + <&ioport6 14 GPIO_ACTIVE_HIGH>, /* D50 | RX2 */ |
| 145 | + <&ioport6 11 GPIO_ACTIVE_HIGH>, /* D51 | RTS2 */ |
| 146 | + <&ioport4 4 GPIO_ACTIVE_HIGH>, /* D52 | CTS2 */ |
| 147 | + <&ioport5 6 GPIO_ACTIVE_HIGH>, /* D53 | TX3 */ |
| 148 | + <&ioport3 4 GPIO_ACTIVE_HIGH>, /* D54 | RX3 */ |
| 149 | + <&ioport5 3 GPIO_ACTIVE_HIGH>, /* D55 | RTS3 */ |
| 150 | + <&ioport5 2 GPIO_ACTIVE_HIGH>, /* D56 | CTS3 */ |
| 151 | + <&ioport8 5 GPIO_ACTIVE_HIGH>, /* D57 | TX4 */ |
| 152 | + <&ioport5 13 GPIO_ACTIVE_HIGH>, /* D58 | RX4 */ |
| 153 | + <&ioport5 8 GPIO_ACTIVE_HIGH>, /* D59 | RTS4 */ |
| 154 | + <&ioport5 5 GPIO_ACTIVE_HIGH>, /* D60 | CTS4 */ |
| 155 | + <&ioport6 3 GPIO_ACTIVE_HIGH>, /* D61 | RTS0 */ |
| 156 | + <&ioport6 4 GPIO_ACTIVE_HIGH>, /* D62 | CTS0 */ |
| 157 | + |
| 158 | + // SSI (Audio) |
| 159 | + <&ioport1 12 GPIO_ACTIVE_HIGH>, /* D63 | SSI CK */ |
| 160 | + <&ioport1 13 GPIO_ACTIVE_HIGH>, /* D64 | SSI WS */ |
| 161 | + <&ioport1 14 GPIO_ACTIVE_HIGH>, /* D65 | SSI SDI */ |
| 162 | + <&ioport1 15 GPIO_ACTIVE_HIGH>, /* D66 | SSI SDO */ |
| 163 | + |
| 164 | + // Generic GPIO pins |
| 165 | + <&ioport9 8 GPIO_ACTIVE_HIGH>, /* D67 | */ |
| 166 | + <&ioport4 3 GPIO_ACTIVE_HIGH>, /* D68 | */ |
| 167 | + <&ioport9 1 GPIO_ACTIVE_HIGH>, /* D69 | */ |
| 168 | + <&ioport6 12 GPIO_ACTIVE_HIGH>, /* D70 | */ |
| 169 | + <&ioport3 12 GPIO_ACTIVE_HIGH>, /* D71 | */ |
| 170 | + <&ioport3 13 GPIO_ACTIVE_HIGH>, /* D72 | */ |
| 171 | + <&ioport3 14 GPIO_ACTIVE_HIGH>, /* D73 | */ |
| 172 | + <&ioporta 1 GPIO_ACTIVE_HIGH>, /* D74 | */ |
| 173 | + <&ioporta 8 GPIO_ACTIVE_HIGH>, /* D75 | */ |
| 174 | + <&ioporta 9 GPIO_ACTIVE_HIGH>, /* D76 | */ |
| 175 | + <&ioporta 10 GPIO_ACTIVE_HIGH>, /* D77 | */ |
| 176 | + <&ioport5 7 GPIO_ACTIVE_HIGH>, /* D78 | */ |
| 177 | + <&ioportb 0 GPIO_ACTIVE_HIGH>, /* D79 | */ |
| 178 | + <&ioport6 15 GPIO_ACTIVE_HIGH>, /* D80 | */ |
| 179 | + <&ioport0 3 GPIO_ACTIVE_HIGH>, /* D81 | */ |
| 180 | + <&ioport0 7 GPIO_ACTIVE_HIGH>, /* D82 | */ |
| 181 | + <&ioport0 8 GPIO_ACTIVE_HIGH>, /* D83 | */ |
| 182 | + |
| 183 | + // SDCARD |
| 184 | + <&ioport4 13 GPIO_ACTIVE_HIGH>, /* D84 | SDHI CLK */ |
| 185 | + <&ioport4 12 GPIO_ACTIVE_HIGH>, /* D85 | SDHI CMD */ |
| 186 | + <&ioport4 11 GPIO_ACTIVE_HIGH>, /* D86 | SDHI D0 */ |
| 187 | + <&ioport4 10 GPIO_ACTIVE_HIGH>, /* D87 | SDHI D1 */ |
| 188 | + <&ioport2 6 GPIO_ACTIVE_HIGH>, /* D88 | SDHI D2 */ |
| 189 | + <&ioport2 5 GPIO_ACTIVE_HIGH>, /* D89 | SDHI D3 */ |
| 190 | + <&ioport4 15 GPIO_ACTIVE_HIGH>, /* D90 | SDHI CD */ |
| 191 | + <&ioport4 14 GPIO_ACTIVE_HIGH>; /* D91 | SDHI WP */ |
| 192 | + |
| 193 | + |
68 | 194 |
|
69 | 195 | builtin-led-gpios = <&ioport1 7 GPIO_ACTIVE_LOW>,
|
70 | 196 | <&ioport4 0 GPIO_ACTIVE_LOW>,
|
71 | 197 | <&ioport8 0 GPIO_ACTIVE_LOW>;
|
72 | 198 |
|
73 | 199 | pwm-pin-gpios = <&ioport6 0 0>;
|
74 | 200 |
|
75 |
| - serials = <&board_cdc_acm_uart>, <&uart9>; |
| 201 | + serials = <&board_cdc_acm_uart>, <&uart9>, <&uart7>, <&uart6>, <&uart5>; |
76 | 202 | cdc-acm = <&board_cdc_acm_uart>;
|
77 | 203 | i2cs = <&iic1>;
|
78 | 204 | spis = <&spi1>;
|
|
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