uDisplay force cache writes to RGB display on ESP32S3

[s-hadinger]

Description:

Fix visible artifacts on ESP32S3 with RGB displays. The problem is caused by cache lines not being flushed after updating the display (the internal memory is updated but writes to PSRAM which stored the frame buffer are delayed until cache lines are reclaimed).

It seems that the previously used esp_cache_msync() does not work anymore, it is replace by Cache_WriteBack_Addr()

Checklist:

• The pull request is done against the latest development branch
• Only relevant files were touched
• Only one feature/fix was added per PR and the code change compiles without warnings
• The code change is tested and works with Tasmota core ESP8266 V.2.7.8
• The code change is tested and works with Tasmota core ESP32 V.3.1.0.240926
• I accept the CLA.

NOTE: The code change must pass CI tests. Your PR cannot be merged unless tests pass