What is the dot clock's timing source?

[ReiquelApplegate]

In ares/sfc/ppu/counter/inline.hpp:

//one PPU dot = 4 CPU clocks.
//
//PPU dots 323 and 327 are 6 CPU clocks long.

According to fullsnes the dot clock is the master clock divided by 4, not the cpu clock divided by 4. If it were the cpu clock wouldn't switching between fastrom/slowrom change how many dots appear on a scanline?

[LukeUsher]

SlowROM and FastROM do not change the cpu clock itself but the ROM access speed; this still has the effect of slowing down execution but doesn’t impact other timing. Specifically the cpu inserts additional wait states when accessing slow ROM to give it chance to stabilise.

See

ares/ares/sfc/cpu/memory.cpp

Line 30 in dac6a20

alwaysinline auto CPU::wait(n24 address) const -> u32 {

[ReiquelApplegate]

CPU::wait can return either 6, 8, or 12. Aren't those the number of master cycles a single CPU cycle takes?

[LukeUsher]

The first branch in wait specifically takes romspeed into account; where romspeed is set to the number of wait states configured for the memory region.

[ReiquelApplegate]

Yes but shouldn't the comment instead read:

//one PPU dot = 4 master cycles .
//
//PPU dots 323 and 327 are 6 master cycles long.

This quote from the emu author is why I think that:

(for others: a cycle is 6, 8 or 12 master clocks depending on the memory area and FastROM setting)

source: https://forums.nesdev.org/viewtopic.php?p=104265#p104265