7575-include_lib (" jit.hrl" ).
7676
7777-include (" primitives.hrl" ).
78+ -include (" term.hrl" ).
7879
7980-define (ASSERT (Expr ), true = Expr ).
8081
@@ -1310,7 +1311,7 @@ if_block_cond(
13101311 I1 = jit_armv6m_asm :mov (Temp , Reg ),
13111312 Stream1 = StreamModule :append (Stream0 , I1 ),
13121313 State1 = State0 # state {stream = Stream1 },
1313- State2 = and_ (State1 # state {available_regs = AT }, Temp , Mask ),
1314+ { State2 , Temp } = and_ (State1 # state {available_regs = AT }, { free , Temp } , Mask ),
13141315 Stream2 = State2 # state .stream ,
13151316 % Compare with value
13161317 I2 = jit_armv6m_asm :cmp (Temp , Val ),
@@ -1329,7 +1330,7 @@ if_block_cond(
13291330) when ? IS_GPR (Reg ) ->
13301331 % AND with mask
13311332 OffsetBefore = StreamModule :offset (Stream0 ),
1332- State1 = and_ (State0 , Reg , Mask ),
1333+ { State1 , Reg } = and_ (State0 , RegTuple , Mask ),
13331334 Stream1 = State1 # state .stream ,
13341335 % Compare with value
13351336 I2 = jit_armv6m_asm :cmp (Reg , Val ),
@@ -2517,34 +2518,34 @@ get_module_index(
25172518% % JIT currentl calls this with two values: ?TERM_PRIMARY_CLEAR_MASK (-4) to
25182519% % clear bits and ?TERM_BOXED_TAG_MASK (0x3F). We can avoid any literal pool
25192520% % by using BICS for -4.
2520- and_ (# state {stream_module = StreamModule , stream = Stream0 } = State0 , Reg , 16#FFFFFF ) ->
2521+ and_ (# state {stream_module = StreamModule , stream = Stream0 } = State0 , { free , Reg } , 16#FFFFFF ) ->
25212522 I1 = jit_armv6m_asm :lsls (Reg , Reg , 8 ),
25222523 I2 = jit_armv6m_asm :lsrs (Reg , Reg , 8 ),
25232524 Stream1 = StreamModule :append (Stream0 , <<I1 /binary , I2 /binary >>),
2524- State0 # state {stream = Stream1 };
2525+ { State0 # state {stream = Stream1 }, Reg };
25252526and_ (
25262527 # state {stream_module = StreamModule , available_regs = [Temp | AT ]} = State0 ,
2527- Reg ,
2528+ { free , Reg } ,
25282529 Val
25292530) when Val < 0 andalso Val >= - 256 ->
25302531 State1 = mov_immediate (State0 # state {available_regs = AT }, Temp , bnot (Val )),
25312532 Stream1 = State1 # state .stream ,
25322533 I = jit_armv6m_asm :bics (Reg , Temp ),
25332534 Stream2 = StreamModule :append (Stream1 , I ),
2534- State1 # state {available_regs = [Temp | AT ], stream = Stream2 };
2535+ { State1 # state {available_regs = [Temp | AT ], stream = Stream2 }, Reg };
25352536and_ (
25362537 # state {stream_module = StreamModule , available_regs = [Temp | AT ]} = State0 ,
2537- Reg ,
2538+ { free , Reg } ,
25382539 Val
25392540) ->
25402541 State1 = mov_immediate (State0 # state {available_regs = AT }, Temp , Val ),
25412542 Stream1 = State1 # state .stream ,
25422543 I = jit_armv6m_asm :ands (Reg , Temp ),
25432544 Stream2 = StreamModule :append (Stream1 , I ),
2544- State1 # state {available_regs = [Temp | AT ], stream = Stream2 };
2545+ { State1 # state {available_regs = [Temp | AT ], stream = Stream2 }, Reg };
25452546and_ (
25462547 # state {stream_module = StreamModule , available_regs = []} = State0 ,
2547- Reg ,
2548+ { free , Reg } ,
25482549 Val
25492550) when Val < 0 andalso Val >= - 256 ->
25502551 % No available registers, use r0 as temp and save it to r12
@@ -2561,10 +2562,10 @@ and_(
25612562 % Restore r0 from r12
25622563 Restore = jit_armv6m_asm :mov (r0 , ? IP_REG ),
25632564 Stream4 = StreamModule :append (Stream3 , Restore ),
2564- State0 # state {stream = Stream4 };
2565+ { State0 # state {stream = Stream4 }, Reg };
25652566and_ (
25662567 # state {stream_module = StreamModule , available_regs = []} = State0 ,
2567- Reg ,
2568+ { free , Reg } ,
25682569 Val
25692570) ->
25702571 % No available registers, use r0 as temp and save it to r12
@@ -2581,7 +2582,17 @@ and_(
25812582 % Restore r0 from r12
25822583 Restore = jit_armv6m_asm :mov (r0 , ? IP_REG ),
25832584 Stream4 = StreamModule :append (Stream3 , Restore ),
2584- State0 # state {stream = Stream4 }.
2585+ {State0 # state {stream = Stream4 }, Reg };
2586+ and_ (
2587+ # state {stream_module = StreamModule , available_regs = [ResultReg | AT ], used_regs = UR } =
2588+ State0 ,
2589+ Reg ,
2590+ ? TERM_PRIMARY_CLEAR_MASK
2591+ ) ->
2592+ I1 = jit_armv6m_asm :lsrs (ResultReg , Reg , 2 ),
2593+ I2 = jit_armv6m_asm :lsls (ResultReg , ResultReg , 2 ),
2594+ Stream1 = StreamModule :append (State0 # state .stream , <<I1 /binary , I2 /binary >>),
2595+ {State0 # state {stream = Stream1 , available_regs = AT , used_regs = [ResultReg | UR ]}, ResultReg }.
25852596
25862597or_ (
25872598 # state {stream_module = StreamModule , available_regs = [Temp | AT ]} = State0 ,
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