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x86 FPU: add semantics for all x86 FPU instructions #394

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PeterMatula opened this issue Sep 12, 2018 · 2 comments
Closed

x86 FPU: add semantics for all x86 FPU instructions #394

PeterMatula opened this issue Sep 12, 2018 · 2 comments
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@JurajHolub
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C-capstone2llvmir enhancement T-arch-x86-fpu T-arch-x86
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RetDec v4

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@PeterMatula
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While working on #293 I noticed some x86 FPU instructions are not modeled in capstone2llvmir. As discussed in #193, not all of them have to be fully translated into LLVM IR. Also, there might be some already modeled instructions that would be better represented with intrinsic function calls or pseudo assembly function calls. But all of these need to be analyzed and decided how to best represent them. Once decided, I might add info on what to do to every instruction in this list.

List of x86 FPU missing instructions:

  • F2XM1
  • FBLD
  • FBSTP
  • FNCLEX
  • FCMOVcc
  • FFREE
  • FISTTP
  • FLDCW
  • FLDENV
  • FPATAN
  • FPREM
  • FPREM1
  • FPTAN
  • FRSTOR
  • FNSAVE
  • FSCALE
  • FNSTCW
  • FNSTENV
  • FNSTSW
  • FXAM
  • FXRSTOR
  • FXRSTOR64
  • FXSAVE
  • FXSAVE64
  • FXTRACT
  • FYL2X
  • FYL2XP1
@PeterMatula PeterMatula added this to the x86 floating point support (FPU, MMX, SSE, etc.) milestone Sep 12, 2018
@PeterMatula
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This issue might get solved as part of a bachelor thesis - see milestone.

@PeterMatula PeterMatula removed this from the x86 floating point support (FPU, MMX, SSE, etc.) milestone Sep 12, 2019
@PeterMatula PeterMatula mentioned this issue Sep 12, 2019
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@PeterMatula
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Will be solved by #643.
See #643 (comment) for implementation details.

@PeterMatula PeterMatula added this to the RetDec v4 milestone Sep 16, 2019
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@JurajHolub JurajHolub

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C-capstone2llvmir enhancement T-arch-x86-fpu T-arch-x86
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RetDec v4
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