verilog code reading error

[sun123-cmd]

I' m trying to read adder.v verilog code with abc tool:

  1 module adder (
  2     input [7:0] a,
  3     input [7:0] b,
  4     output [7:0] sum
  5 );
  6     wire [8:0] carry;
  7     assign carry = a + b;
  8     assign sum = carry[7:0];
  9 endmodule

However, abc quit with error:

abc 01> read adder.v
abc: /home/sun/Desktop/abc/src/base/ver/verCore.c:429: Ver_ParseModule: Assertion `Symbol == ')'' failed.
Aborted (core dumped)

I wonder how to solve this error.