ABC interpetation of a XOR gate with complementary input for technology mapping

[jasperzw]

I am working on a project involving efficient synthesis for a novel beyond-CMOS gate technology. In this technology, XOR gates require a complementary (inverted) version of one of their two inputs. Currently, I am adding an explicit inverter to each XOR gate implementation, which works fine during technology mapping when using ABC called from Yosys.

However, in this new technology, inverters are almost as large in area as the XOR gate itself (which requires the inverted input). To optimize area, I would like to focus on sharing inverters between XOR gates where possible or invert any constant logic. For this, I created a gate in the Liberty file as follows:

cell(xor_test) {
  area :  1;
  cell_footprint : XOR_4T;
/*  cell_description : "T 2-Input XOR based on 2 times 4T devices needs an inverted input"; */
  pg_pin (VCC) {
    pg_type : primary_power;
    voltage_name : "VCC";
  }
  pg_pin (GND) {
    pg_type : primary_ground;
    voltage_name : "GND";
  }
  pin (a) {
    direction : "input";
    related_ground_pin : GND;
    related_power_pin : VCC;
    capacitance : 1;
  }
  pin (b) {
    direction : "input";
    related_ground_pin : GND;
    related_power_pin : VCC;
    capacitance : 1;
  }
  pin (b_bar) {
    direction : "input";
    related_ground_pin : GND;
    related_power_pin : VCC;Q
    capacitance : 1;
  }
  pin (out) {
    direction : "output";
    related_ground_pin : GND;
    related_power_pin : VCC;
    function : "(a&b_bar)|(!(a)&b)";
    max_fanout : 10;
    timing () {....}
    timing () {....}
  pin_opposite("b","b_bar");
}

In this design, the input b_bar is the complement of b. However, ABC does not seem to make use of this gate, even though the area is set to 1 to strongly incentivize its use. My goal is to have ABC utilize the pin_opposite property to optimize for inverter sharing across XOR gates instead of adding individual inverters to each instance.

My Questions:

• Does ABC support the pin_opposite property from the Liberty file format? If so, how can I configure ABC to recognize and apply this property during technology mapping?

• How can I modify the synthesis flow or ABC script to ensure that this custom XOR gate (xor_test) is prioritized and used efficiently?

The ABC script I am using for technology mapping is as follows:

 strash; show; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash;
       &get -n; show; &dch -f; &nf {D}; &put; show -g

Any insights on how to proceed with integrating the pin_opposite functionality into ABC or other suggestions to improve inverter sharing would be amazing and thank you a head in time.