LimeSDR-PCIE_lms7_trx.qsf

set_global_assignment -name FITTER_EFFORT "AUTO FIT"
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus II License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors.  Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
# Date created = 13:31:32  June 04, 2015
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		LimeSDR-PCIE_lms7_trx_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:gui.tcl"
set_global_assignment -name FAMILY "Cyclone IV GX"
set_global_assignment -name DEVICE EP4CGX30CF23C7
set_global_assignment -name TOP_LEVEL_ENTITY lms7_trx_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:49:17  JUNE 03, 2016"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_location_assignment PIN_M21 -to CLK50_FPGA
set_location_assignment PIN_F2 -to PCIE_HSI_IC[3]
set_location_assignment PIN_K2 -to PCIE_HSI_IC[2]
set_location_assignment PIN_P2 -to PCIE_HSI_IC[1]
set_location_assignment PIN_V2 -to PCIE_HSI_IC[0]
set_location_assignment PIN_F1 -to "PCIE_HSI_IC[3](n)"
set_location_assignment PIN_K1 -to "PCIE_HSI_IC[2](n)"
set_location_assignment PIN_P1 -to "PCIE_HSI_IC[1](n)"
set_location_assignment PIN_V1 -to "PCIE_HSI_IC[0](n)"
set_location_assignment PIN_H2 -to PCIE_HSO[3]
set_location_assignment PIN_M2 -to PCIE_HSO[2]
set_location_assignment PIN_T2 -to PCIE_HSO[1]
set_location_assignment PIN_Y2 -to PCIE_HSO[0]
set_location_assignment PIN_H1 -to "PCIE_HSO[3](n)"
set_location_assignment PIN_M1 -to "PCIE_HSO[2](n)"
set_location_assignment PIN_T1 -to "PCIE_HSO[1](n)"
set_location_assignment PIN_Y1 -to "PCIE_HSO[0](n)"
set_location_assignment PIN_H12 -to PCIE_PERSTN
set_location_assignment PIN_M7 -to PCIE_REFCLK
set_location_assignment PIN_N7 -to "PCIE_REFCLK(n)"
set_location_assignment PIN_H21 -to FPGA_LED1_G
set_location_assignment PIN_E20 -to FPGA_LED1_R
set_location_assignment PIN_G20 -to FPGA_LED2_G
set_location_assignment PIN_G21 -to FPGA_LED2_R
set_location_assignment PIN_B1 -to FPGA_SPI0_LMS_SS
set_location_assignment PIN_A3 -to FPGA_SPI0_MISO
set_location_assignment PIN_C1 -to FPGA_SPI0_MOSI
set_location_assignment PIN_B3 -to FPGA_SPI0_SCLK
set_location_assignment PIN_E6 -to LMS_DIQ1_D[11]
set_location_assignment PIN_F8 -to LMS_DIQ1_D[10]
set_location_assignment PIN_G7 -to LMS_DIQ1_D[9]
set_location_assignment PIN_E8 -to LMS_DIQ1_D[8]
set_location_assignment PIN_G8 -to LMS_DIQ1_D[7]
set_location_assignment PIN_H7 -to LMS_DIQ1_D[6]
set_location_assignment PIN_C9 -to LMS_DIQ1_D[5]
set_location_assignment PIN_C7 -to LMS_DIQ1_D[4]
set_location_assignment PIN_C8 -to LMS_DIQ1_D[3]
set_location_assignment PIN_H8 -to LMS_DIQ1_D[2]
set_location_assignment PIN_B7 -to LMS_DIQ1_D[1]
set_location_assignment PIN_D9 -to LMS_DIQ1_D[0]
set_location_assignment PIN_D6 -to LMS_DIQ1_IQSEL
set_location_assignment PIN_A6 -to LMS_DIQ2_D[11]
set_location_assignment PIN_B4 -to LMS_DIQ2_D[10]
set_location_assignment PIN_D5 -to LMS_DIQ2_D[9]
set_location_assignment PIN_A5 -to LMS_DIQ2_D[8]
set_location_assignment PIN_D4 -to LMS_DIQ2_D[7]
set_location_assignment PIN_C6 -to LMS_DIQ2_D[6]
set_location_assignment PIN_F6 -to LMS_DIQ2_D[5]
set_location_assignment PIN_D8 -to LMS_DIQ2_D[4]
set_location_assignment PIN_D7 -to LMS_DIQ2_D[3]
set_location_assignment PIN_A8 -to LMS_DIQ2_D[2]
set_location_assignment PIN_E5 -to LMS_DIQ2_D[1]
set_location_assignment PIN_G6 -to LMS_DIQ2_D[0]
set_location_assignment PIN_B6 -to LMS_DIQ2_IQSEL2
set_location_assignment PIN_H9 -to LMS_FCLK1
set_location_assignment PIN_C5 -to LMS_FCLK2
set_location_assignment PIN_K10 -to LMS_MCLK1
set_location_assignment PIN_A1 -to LMS_RESET
set_location_assignment PIN_J15 -to EXT_GND
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS64
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHZ
set_location_assignment PIN_AA12 -to CLK100_FPGA
set_location_assignment PIN_B19 -to FPGA_SPI1_ADF_SS
set_location_assignment PIN_A20 -to FPGA_SPI1_DAC_SS
set_location_assignment PIN_C19 -to FPGA_SPI1_MOSI
set_location_assignment PIN_C20 -to FPGA_SPI1_SCLK
set_location_assignment PIN_K20 -to FPGA_LED3
set_location_assignment PIN_K19 -to FPGA_LED4
set_location_assignment PIN_K22 -to FPGA_LED5
set_location_assignment PIN_H20 -to FPGA_LED6
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE debug.stp
set_location_assignment PIN_G16 -to FPGA_I2C_SDA
set_location_assignment PIN_G17 -to FPGA_I2C_SCL
set_location_assignment PIN_J4 -to FPGA_AS_NCSO
set_location_assignment PIN_D3 -to FPGA_AS_DCLK
set_location_assignment PIN_K4 -to FPGA_AS_DATA0
set_location_assignment PIN_D1 -to FPGA_AS_ASDO
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_location_assignment PIN_K13 -to FAN_CTRL
set_location_assignment PIN_K14 -to LM75_OS
set_location_assignment PIN_F18 -to ADF_MUXOUT
set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:gen_prg_files.tcl"
set_global_assignment -name SEARCH_PATH symbols/
set_location_assignment PIN_A14 -to BOM_VER[3]
set_location_assignment PIN_A13 -to BOM_VER[2]
set_location_assignment PIN_A19 -to BOM_VER[1]
set_location_assignment PIN_A18 -to BOM_VER[0]
set_location_assignment PIN_A12 -to HW_VER[3]
set_location_assignment PIN_A11 -to HW_VER[2]
set_location_assignment PIN_C10 -to HW_VER[1]
set_location_assignment PIN_H14 -to HW_VER[0]
set_location_assignment PIN_A21 -to TX1_2_LB_H
set_location_assignment PIN_A22 -to TX1_2_LB_L
set_location_assignment PIN_B20 -to TX1_2_LB_SH
set_location_assignment PIN_B21 -to TX2_2_LB_H
set_location_assignment PIN_B22 -to TX2_2_LB_L
set_location_assignment PIN_C22 -to TX2_2_LB_SH
set_location_assignment PIN_A4 -to LMS_TXNRX2
set_location_assignment PIN_C3 -to LMS_TXNRX1
set_location_assignment PIN_A7 -to LMS_TXEN
set_location_assignment PIN_C2 -to LMS_RXEN
set_location_assignment PIN_C4 -to LMS_CORE_LDO_EN
set_location_assignment PIN_Y22 -to DDR2_1_ADDR[12]
set_location_assignment PIN_U22 -to DDR2_1_ADDR[11]
set_location_assignment PIN_AB17 -to DDR2_1_ADDR[10]
set_location_assignment PIN_AB21 -to DDR2_1_ADDR[9]
set_location_assignment PIN_V22 -to DDR2_1_ADDR[8]
set_location_assignment PIN_AA20 -to DDR2_1_ADDR[7]
set_location_assignment PIN_W22 -to DDR2_1_ADDR[6]
set_location_assignment PIN_AB20 -to DDR2_1_ADDR[5]
set_location_assignment PIN_V21 -to DDR2_1_ADDR[4]
set_location_assignment PIN_AB19 -to DDR2_1_ADDR[3]
set_location_assignment PIN_AA21 -to DDR2_1_ADDR[2]
set_location_assignment PIN_AA19 -to DDR2_1_ADDR[1]
set_location_assignment PIN_W20 -to DDR2_1_ADDR[0]
set_location_assignment PIN_U20 -to DDR2_1_BA[2]
set_location_assignment PIN_R20 -to DDR2_1_BA[1]
set_location_assignment PIN_T20 -to DDR2_1_BA[0]
set_location_assignment PIN_P22 -to DDR2_1_CAS_N
set_location_assignment PIN_T19 -to DDR2_1_CKE[0]
set_location_assignment PIN_R9 -to DDR2_1_CLK[0]
set_location_assignment PIN_T9 -to DDR2_1_CLK_N[0]
set_location_assignment PIN_T22 -to DDR2_1_CS_N[0]
set_location_assignment PIN_U15 -to DDR2_1_DM[1]
set_location_assignment PIN_R13 -to DDR2_1_DM[0]
set_location_assignment PIN_W17 -to DDR2_1_DQ[15]
set_location_assignment PIN_Y19 -to DDR2_1_DQ[14]
set_location_assignment PIN_Y18 -to DDR2_1_DQ[13]
set_location_assignment PIN_Y16 -to DDR2_1_DQ[12]
set_location_assignment PIN_Y15 -to DDR2_1_DQ[11]
set_location_assignment PIN_AA18 -to DDR2_1_DQ[10]
set_location_assignment PIN_AA16 -to DDR2_1_DQ[9]
set_location_assignment PIN_AB18 -to DDR2_1_DQ[8]
set_location_assignment PIN_W15 -to DDR2_1_DQ[7]
set_location_assignment PIN_W14 -to DDR2_1_DQ[6]
set_location_assignment PIN_W13 -to DDR2_1_DQ[5]
set_location_assignment PIN_Y14 -to DDR2_1_DQ[4]
set_location_assignment PIN_Y13 -to DDR2_1_DQ[3]
set_location_assignment PIN_AB15 -to DDR2_1_DQ[2]
set_location_assignment PIN_AB14 -to DDR2_1_DQ[1]
set_location_assignment PIN_AB10 -to DDR2_1_DQ[0]
set_location_assignment PIN_AA15 -to DDR2_1_DQS[1]
set_location_assignment PIN_T13 -to DDR2_1_DQS[0]
set_location_assignment PIN_R21 -to DDR2_1_ODT[0]
set_location_assignment PIN_T21 -to DDR2_1_RAS_N
set_location_assignment PIN_V20 -to DDR2_1_WE_N
set_location_assignment PIN_B9 -to LMK_CLK
set_location_assignment PIN_N11 -to SI_CLK3
set_location_assignment PIN_M22 -to SI_CLK6
set_location_assignment PIN_M11 -to LMS_MCLK2
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name DEVICE_MIGRATION_LIST "EP4CGX30CF23C7,EP4CGX50CF23C7"
set_location_assignment PIN_N17 -to DDR2_2_ADDR[12]
set_location_assignment PIN_N14 -to DDR2_2_ADDR[11]
set_location_assignment PIN_R15 -to DDR2_2_ADDR[10]
set_location_assignment PIN_P15 -to DDR2_2_ADDR[9]
set_location_assignment PIN_P13 -to DDR2_2_ADDR[8]
set_location_assignment PIN_M16 -to DDR2_2_ADDR[7]
set_location_assignment PIN_M15 -to DDR2_2_ADDR[6]
set_location_assignment PIN_N15 -to DDR2_2_ADDR[5]
set_location_assignment PIN_N13 -to DDR2_2_ADDR[4]
set_location_assignment PIN_T11 -to DDR2_2_ADDR[3]
set_location_assignment PIN_M14 -to DDR2_2_ADDR[2]
set_location_assignment PIN_P14 -to DDR2_2_ADDR[1]
set_location_assignment PIN_M13 -to DDR2_2_ADDR[0]
set_location_assignment PIN_AA4 -to DDR2_2_BA[2]
set_location_assignment PIN_AA13 -to DDR2_2_BA[1]
set_location_assignment PIN_AB13 -to DDR2_2_BA[0]
set_location_assignment PIN_R19 -to DDR2_2_CAS_N
set_location_assignment PIN_T14 -to DDR2_2_CKE[0]
set_location_assignment PIN_W4 -to DDR2_2_CLK[0]
set_location_assignment PIN_Y4 -to DDR2_2_CLK_N[0]
set_location_assignment PIN_AB11 -to DDR2_2_CS_N[0]
set_location_assignment PIN_W12 -to DDR2_2_DM[1]
set_location_assignment PIN_W7 -to DDR2_2_DM[0]
set_location_assignment PIN_AA10 -to DDR2_2_DQ[15]
set_location_assignment PIN_Y11 -to DDR2_2_DQ[14]
set_location_assignment PIN_W11 -to DDR2_2_DQ[13]
set_location_assignment PIN_AB8 -to DDR2_2_DQ[12]
set_location_assignment PIN_AA9 -to DDR2_2_DQ[11]
set_location_assignment PIN_Y9 -to DDR2_2_DQ[10]
set_location_assignment PIN_W9 -to DDR2_2_DQ[9]
set_location_assignment PIN_AB6 -to DDR2_2_DQ[8]
set_location_assignment PIN_W6 -to DDR2_2_DQ[7]
set_location_assignment PIN_W5 -to DDR2_2_DQ[6]
set_location_assignment PIN_Y7 -to DDR2_2_DQ[5]
set_location_assignment PIN_Y6 -to DDR2_2_DQ[4]
set_location_assignment PIN_Y5 -to DDR2_2_DQ[3]
set_location_assignment PIN_AA6 -to DDR2_2_DQ[2]
set_location_assignment PIN_AB5 -to DDR2_2_DQ[1]
set_location_assignment PIN_AB4 -to DDR2_2_DQ[0]
set_location_assignment PIN_Y10 -to DDR2_2_DQS[1]
set_location_assignment PIN_Y8 -to DDR2_2_DQS[0]
set_location_assignment PIN_W18 -to DDR2_2_ODT[0]
set_location_assignment PIN_U14 -to DDR2_2_RAS_N
set_location_assignment PIN_T15 -to DDR2_2_WE_N
set_location_assignment PIN_L21 -to SI_CLK0
set_location_assignment PIN_L22 -to SI_CLK1
set_location_assignment PIN_J10 -to SI_CLK2
set_location_assignment PIN_A9 -to SI_CLK5
set_location_assignment PIN_AB12 -to SI_CLK7
set_location_assignment PIN_M8 -to CLK125_FPGA
set_location_assignment PIN_N8 -to "CLK125_FPGA(n)"
set_global_assignment -name SEED 2
set_location_assignment PIN_D22 -to FPGA_SW[0]
set_location_assignment PIN_E21 -to FPGA_SW[1]
set_location_assignment PIN_E22 -to FPGA_SW[2]
set_location_assignment PIN_G22 -to FPGA_SW[3]
set_location_assignment PIN_C13 -to FPGA_GPIO[15]
set_location_assignment PIN_C12 -to FPGA_GPIO[14]
set_location_assignment PIN_C15 -to FPGA_GPIO[13]
set_location_assignment PIN_C14 -to FPGA_GPIO[12]
set_location_assignment PIN_D15 -to FPGA_GPIO[11]
set_location_assignment PIN_D14 -to FPGA_GPIO[10]
set_location_assignment PIN_G15 -to FPGA_GPIO[8]
set_location_assignment PIN_A16 -to FPGA_GPIO[7]
set_location_assignment PIN_A17 -to FPGA_GPIO[6]
set_location_assignment PIN_B16 -to FPGA_GPIO[5]
set_location_assignment PIN_A15 -to FPGA_GPIO[4]
set_location_assignment PIN_B13 -to FPGA_GPIO[3]
set_location_assignment PIN_B15 -to FPGA_GPIO[2]
set_location_assignment PIN_C16 -to FPGA_GPIO[1]
set_location_assignment PIN_B12 -to FPGA_GPIO[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to CLK50_FPGA
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_HSI_IC[3]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_HSI_IC[2]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_HSI_IC[1]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_HSI_IC[0]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_HSO[3]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_HSO[2]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_HSO[1]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_HSO[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PCIE_PERSTN
set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to EXT_GND
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_RESET
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_FCLK2
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_FCLK1
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ2_IQSEL2
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ2_D[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ2_D[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ2_D[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ2_D[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ2_D[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ2_D[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ2_D[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ2_D[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ2_D[8]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ2_D[9]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ2_D[10]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ2_D[11]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ1_IQSEL
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ1_D[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ1_D[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ1_D[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ1_D[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ1_D[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ1_D[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ1_D[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ1_D[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ1_D[8]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ1_D[9]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ1_D[10]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_DIQ1_D[11]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_MCLK1
set_instance_assignment -name IO_STANDARD "1.8 V" -to CLK100_FPGA
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_LED1_G
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_LED1_R
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_LED2_G
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_LED2_R
set_instance_assignment -name IO_STANDARD "2.5 V" -to FPGA_SPI0_LMS_SS
set_instance_assignment -name IO_STANDARD "2.5 V" -to FPGA_SPI0_MISO
set_instance_assignment -name IO_STANDARD "2.5 V" -to FPGA_SPI0_MOSI
set_instance_assignment -name IO_STANDARD "2.5 V" -to FPGA_SPI0_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_SPI1_ADF_SS
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_SPI1_DAC_SS
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_SPI1_MOSI
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_SPI1_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_LED3
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_LED4
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_LED5
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_LED6
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to CLK50_FPGA
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_I2C_SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_I2C_SCL
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_AS_NCSO
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_AS_DCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_AS_DATA0
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_AS_ASDO
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FAN_CTRL
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LM75_OS
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ADF_MUXOUT
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to BOM_VER[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to BOM_VER[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to BOM_VER[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to BOM_VER[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HW_VER[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HW_VER[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HW_VER[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HW_VER[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_2_LB_H
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_2_LB_L
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_2_LB_SH
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX2_2_LB_H
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX2_2_LB_L
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX2_2_LB_SH
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_ODT[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_ODT[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_CLK[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_CLK[0]
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to DDR2_1_CLK[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_CLK_N[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_CLK_N[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_CS_N[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_CS_N[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_CKE[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_CKE[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_ADDR[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_ADDR[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_ADDR[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_ADDR[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_ADDR[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_ADDR[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_ADDR[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_ADDR[3]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_ADDR[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_ADDR[4]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_ADDR[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_ADDR[5]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_ADDR[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_ADDR[6]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_ADDR[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_ADDR[7]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_ADDR[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_ADDR[8]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_ADDR[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_ADDR[9]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_ADDR[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_ADDR[10]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_ADDR[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_ADDR[11]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_ADDR[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_ADDR[12]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_BA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_BA[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_BA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_BA[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_BA[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_BA[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_RAS_N
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_RAS_N
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_CAS_N
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_CAS_N
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_WE_N
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_1_WE_N
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_DQ[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_DQ[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_DQ[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_DQ[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_DQ[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_DQ[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_DQ[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_DQ[3]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_DQ[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_DQ[4]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_DQ[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_DQ[5]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_DQ[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_DQ[6]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_DQ[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_DQ[7]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_DQ[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_DQ[8]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_DQ[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_DQ[9]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_DQ[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_DQ[10]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_DQ[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_DQ[11]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_DQ[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_DQ[12]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_DQ[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_DQ[13]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_DQ[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_DQ[14]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_DQ[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_DQ[15]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_DQS[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_DQS[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_DQS[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_DQS[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_DM[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_DM[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_1_DM[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_1_DM[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_1_DQ[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_1_DQ[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_1_DQ[2]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_1_DQ[3]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_1_DQ[4]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_1_DQ[5]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_1_DQ[6]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_1_DQ[7]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_1_DQ[8]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_1_DQ[9]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_1_DQ[10]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_1_DQ[11]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_1_DQ[12]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_1_DQ[13]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_1_DQ[14]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_1_DQ[15]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_1_DQ[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_1_DQ[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_1_DQ[2]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_1_DQ[3]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_1_DQ[4]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_1_DQ[5]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_1_DQ[6]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_1_DQ[7]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_1_DQ[8]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_1_DQ[9]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_1_DQ[10]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_1_DQ[11]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_1_DQ[12]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_1_DQ[13]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_1_DQ[14]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_1_DQ[15]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_1_DQS[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_1_DQS[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_1_DQS[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_1_DQS[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_1_DM[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_1_DM[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_1_DM[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_1_DM[1]
set_instance_assignment -name CKN_CK_PAIR ON -from DDR2_1_CLK_N[0] -to DDR2_1_CLK[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_TXNRX2
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_TXEN
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_CORE_LDO_EN
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_RXEN
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_TXNRX1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LMK_CLK
set_instance_assignment -name IO_STANDARD "2.5 V" -to SI_CLK3
set_instance_assignment -name IO_STANDARD "1.8 V" -to SI_CLK6
set_instance_assignment -name IO_STANDARD "2.5 V" -to LMS_MCLK2
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LMS_FCLK1
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LMS_DIQ1_IQSEL
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LMS_DIQ1_D[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LMS_DIQ1_D[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LMS_DIQ1_D[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LMS_DIQ1_D[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LMS_DIQ1_D[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LMS_DIQ1_D[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LMS_DIQ1_D[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LMS_DIQ1_D[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LMS_DIQ1_D[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LMS_DIQ1_D[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LMS_DIQ1_D[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LMS_DIQ1_D[11]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_ODT[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_ODT[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_CLK[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_CLK[0]
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to DDR2_2_CLK[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_CLK_N[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_CLK_N[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_CS_N[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_CS_N[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_CKE[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_CKE[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_ADDR[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_ADDR[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_ADDR[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_ADDR[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_ADDR[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_ADDR[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_ADDR[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_ADDR[3]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_ADDR[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_ADDR[4]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_ADDR[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_ADDR[5]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_ADDR[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_ADDR[6]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_ADDR[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_ADDR[7]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_ADDR[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_ADDR[8]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_ADDR[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_ADDR[9]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_ADDR[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_ADDR[10]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_ADDR[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_ADDR[11]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_ADDR[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_ADDR[12]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_BA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_BA[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_BA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_BA[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_BA[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_BA[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_RAS_N
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_RAS_N
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_CAS_N
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_CAS_N
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_WE_N
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR2_2_WE_N
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_DQ[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_DQ[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_DQ[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_DQ[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_DQ[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_DQ[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_DQ[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_DQ[3]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_DQ[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_DQ[4]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_DQ[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_DQ[5]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_DQ[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_DQ[6]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_DQ[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_DQ[7]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_DQ[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_DQ[8]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_DQ[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_DQ[9]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_DQ[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_DQ[10]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_DQ[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_DQ[11]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_DQ[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_DQ[12]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_DQ[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_DQ[13]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_DQ[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_DQ[14]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_DQ[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_DQ[15]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_DQS[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_DQS[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_DQS[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_DQS[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_DM[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_DM[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to DDR2_2_DM[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR2_2_DM[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_2_DQ[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_2_DQ[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_2_DQ[2]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_2_DQ[3]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_2_DQ[4]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_2_DQ[5]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_2_DQ[6]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_2_DQ[7]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_2_DQ[8]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_2_DQ[9]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_2_DQ[10]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_2_DQ[11]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_2_DQ[12]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_2_DQ[13]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_2_DQ[14]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_2_DQ[15]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_2_DQ[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_2_DQ[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_2_DQ[2]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_2_DQ[3]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_2_DQ[4]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_2_DQ[5]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_2_DQ[6]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_2_DQ[7]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_2_DQ[8]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_2_DQ[9]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_2_DQ[10]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_2_DQ[11]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_2_DQ[12]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_2_DQ[13]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_2_DQ[14]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_2_DQ[15]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_2_DQS[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_2_DQS[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_2_DQS[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_2_DQS[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_2_DM[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to DDR2_2_DM[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_2_DM[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 3078784 -to DDR2_2_DM[1]
set_instance_assignment -name CKN_CK_PAIR ON -from DDR2_2_CLK_N[0] -to DDR2_2_CLK[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SI_CLK0
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SI_CLK1
set_instance_assignment -name IO_STANDARD "2.5 V" -to SI_CLK2
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SI_CLK5
set_instance_assignment -name IO_STANDARD "1.8 V" -to SI_CLK7
set_instance_assignment -name IO_STANDARD LVDS -to CLK125_FPGA
set_instance_assignment -name GLOBAL_SIGNAL OFF -to EXT_GND
set_instance_assignment -name GLOBAL_SIGNAL OFF -to SI_CLK0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to SI_CLK1
set_instance_assignment -name GLOBAL_SIGNAL OFF -to SI_CLK2
set_instance_assignment -name GLOBAL_SIGNAL OFF -to SI_CLK3
set_instance_assignment -name GLOBAL_SIGNAL OFF -to SI_CLK5
set_instance_assignment -name GLOBAL_SIGNAL OFF -to SI_CLK6
set_instance_assignment -name GLOBAL_SIGNAL OFF -to SI_CLK7
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LMS_CORE_LDO_EN
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LMS_RESET
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LMS_RXEN
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LMS_TXEN
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LMS_TXNRX1
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LMS_TXNRX2
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LMS_FCLK2
set_instance_assignment -name SLEW_RATE 2 -to LMS_FCLK2
set_instance_assignment -name SLEW_RATE 2 -to LMS_DIQ1_D[11]
set_instance_assignment -name SLEW_RATE 2 -to LMS_DIQ1_D[10]
set_instance_assignment -name SLEW_RATE 2 -to LMS_DIQ1_D[9]
set_instance_assignment -name SLEW_RATE 2 -to LMS_DIQ1_D[8]
set_instance_assignment -name SLEW_RATE 2 -to LMS_DIQ1_D[7]
set_instance_assignment -name SLEW_RATE 2 -to LMS_DIQ1_D[6]
set_instance_assignment -name SLEW_RATE 2 -to LMS_DIQ1_D[5]
set_instance_assignment -name SLEW_RATE 2 -to LMS_DIQ1_D[4]
set_instance_assignment -name SLEW_RATE 2 -to LMS_DIQ1_D[3]
set_instance_assignment -name SLEW_RATE 2 -to LMS_DIQ1_D[2]
set_instance_assignment -name SLEW_RATE 2 -to LMS_DIQ1_D[1]
set_instance_assignment -name SLEW_RATE 2 -to LMS_DIQ1_D[0]
set_instance_assignment -name SLEW_RATE 2 -to LMS_DIQ1_IQSEL
set_instance_assignment -name SLEW_RATE 2 -to LMS_FCLK1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_SW[3]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to LMS_DIQ1_D[0]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 0 -to LMS_DIQ1_D[1]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to LMS_DIQ1_D[2]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to LMS_DIQ1_D[3]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to LMS_DIQ1_D[4]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to LMS_DIQ1_D[6]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 0 -to LMS_DIQ1_D[7]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 0 -to LMS_DIQ1_D[8]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to LMS_DIQ1_D[9]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to LMS_DIQ1_D[10]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 0 -to LMS_DIQ1_D[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_GPIO[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_GPIO[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_GPIO[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_GPIO[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_GPIO[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_GPIO[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_GPIO[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_GPIO[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_GPIO[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_GPIO[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_GPIO[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_GPIO[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_GPIO[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_GPIO[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_GPIO[1]
set_instance_assignment -name PAD_TO_CORE_DELAY 4 -to LMS_DIQ2_D[11]
set_instance_assignment -name PAD_TO_CORE_DELAY 4 -to LMS_DIQ2_IQSEL2
set_instance_assignment -name PAD_TO_CORE_DELAY 2 -to LMS_DIQ2_D[5]
set_instance_assignment -name PAD_TO_CORE_DELAY 2 -to LMS_DIQ2_D[9]
set_instance_assignment -name PAD_TO_CORE_DELAY 2 -to LMS_DIQ2_D[10]
set_instance_assignment -name PAD_TO_CORE_DELAY 2 -to LMS_DIQ2_D[1]
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION AUTO
set_location_assignment PLL_6 -to "pcie_top:inst2_pcie_top|altpll:altpll_inst0|pll_vhdl_altpll:auto_generated|wire_pll1_clk[1]"
set_global_assignment -name VHDL_FILE src/tx_path_top/pct_separate/synth/pct_separate_fsm.vhd
set_global_assignment -name VHDL_FILE src/tx_path_top/pct_separate/synth/one_pct_fifo.vhd
set_global_assignment -name VHDL_FILE src/rx_path_top/smpl_cnt/synth/iq_smpl_cnt.vhd
set_global_assignment -name VHDL_FILE src/pcie/two_fifo_inst.vhd
set_global_assignment -name VHDL_FILE src/tx_path_top/fifo2diq/synth/txiq_ctrl.vhd
set_global_assignment -name VHDL_FILE src/tx_path_top/packets2data/synth/p2d_rd.vhd
set_global_assignment -name VHDL_FILE src/tx_path_top/pulse_gen/synth/pulse_gen.vhd
set_global_assignment -name VHDL_FILE src/general/general_pkg.vhd
set_global_assignment -name VHDL_FILE src/rxtx_top/synth/rxtx_top.vhd
set_global_assignment -name VHDL_FILE src/general/busy_delay.vhd
set_global_assignment -name VHDL_FILE src/general/FX3_LED_ctrl.vhd
set_global_assignment -name VHDL_FILE src/general_periph/synth/general_periph_top.vhd
set_global_assignment -name VHDL_FILE src/self_test/tst_top.vhd
set_global_assignment -name VHDL_FILE src/spi/pll_ctrl.vhd
set_global_assignment -name VHDL_FILE src/pll_top/pll_top.vhd
set_global_assignment -name VHDL_FILE src/packages/synth/FIFO_PACK.vhd
set_global_assignment -name VHDL_FILE src/spi/tstcfg_pkg.vhd
set_global_assignment -name VHDL_FILE src/spi/pllcfg_pkg.vhd
set_global_assignment -name VHDL_FILE src/spi/periphcfg_pkg.vhd
set_global_assignment -name VHDL_FILE src/spi/fpgacfg_pkg.vhd
set_global_assignment -name VHDL_FILE src/spi/cfg_top.vhd
set_global_assignment -name VHDL_FILE src/top/synth/lms7_trx_top.vhd
set_global_assignment -name VHDL_FILE src/rx_path_top/smpl_cmp/synth/smpl_cmp.vhd
set_global_assignment -name VHDL_FILE src/dyn_ps/synth/pll_ps_top.vhd
set_global_assignment -name VHDL_FILE src/dyn_ps/synth/pll_ps_fsm.vhd
set_global_assignment -name VHDL_FILE src/dyn_ps/synth/pll_ps.vhd
set_global_assignment -name VHDL_FILE src/spi/periphcfg.vhd
set_global_assignment -name VERILOG_FILE ip/pcie_core/pcie_c4_4x_core.v
set_global_assignment -name VERILOG_FILE ip/pcie_core/pcie_c4_4x.v
set_global_assignment -name VHDL_FILE src/tx_path_top/packets2data/synth/packets2data_top.vhd
set_global_assignment -name VHDL_FILE src/tx_path_top/packets2data/synth/packets2data.vhd
set_global_assignment -name VHDL_FILE src/tx_path_top/packets2data/synth/p2d_wr_fsm.vhd
set_global_assignment -name VHDL_FILE src/tx_path_top/packets2data/synth/p2d_sync_fsm.vhd
set_global_assignment -name VHDL_FILE src/tx_path_top/packets2data/synth/p2d_rd_fsm.vhd
set_global_assignment -name VHDL_FILE src/tx_path_top/packets2data/synth/p2d_clr_fsm.vhd
set_global_assignment -name VHDL_FILE src/tx_path_top/bit_unpack/synth/unpack_64_to_64.vhd
set_global_assignment -name VHDL_FILE src/tx_path_top/bit_unpack/synth/unpack_64_to_56.vhd
set_global_assignment -name VHDL_FILE src/tx_path_top/bit_unpack/synth/unpack_64_to_48.vhd
set_global_assignment -name VHDL_FILE src/tx_path_top/bit_unpack/synth/bit_unpack_64.vhd
set_global_assignment -name VHDL_FILE src/tx_pll_top/synth/tx_pll_top.vhd
set_global_assignment -name SDC_FILE LMS7002_timing.sdc
set_global_assignment -name VHDL_FILE src/altera_inst/lpm_cnt_inst.vhd
set_global_assignment -name VHDL_FILE src/rx_path_top/rx_path/synth/rx_path_top.vhd
set_global_assignment -name VHDL_FILE src/rx_path_top/bit_pack/synth/pack_56_to_64.vhd
set_global_assignment -name VHDL_FILE src/rx_path_top/bit_pack/synth/pack_48_to_64.vhd
set_global_assignment -name VHDL_FILE src/rx_path_top/bit_pack/synth/bit_pack.vhd
set_global_assignment -name VHDL_FILE src/rx_pll_top/synth/rx_pll_top.vhd
set_global_assignment -name QIP_FILE ip/clkctrl/clkctrl/synthesis/clkctrl.qip
set_global_assignment -name VHDL_FILE src/txiqmux/synth/txiqmux.vhd
set_global_assignment -name VHDL_FILE src/txiqmux/synth/txiq_tst_ptrn.vhd
set_global_assignment -name VHDL_FILE src/general/sync_reg.vhd
set_global_assignment -name VHDL_FILE src/general/bus_sync_reg.vhd
set_global_assignment -name QIP_FILE ip/pll_rx/pll_rx.qip
set_global_assignment -name QIP_FILE ip/pll_tx/pll_tx.qip
set_global_assignment -name BDF_FILE symbols/pll_block_tx.bdf
set_global_assignment -name BDF_FILE symbols/pll_block_rx.bdf
set_global_assignment -name SDC_FILE lms7_trx_timing.sdc
set_global_assignment -name QIP_FILE ip/ddr2/ddr2.qip
set_global_assignment -name QIP_FILE lms_ctr/synthesis/lms_ctr.qip
set_global_assignment -name VHDL_FILE src/general/FPGA_LED2_ctrl.vhd
set_global_assignment -name VHDL_FILE src/general/FPGA_LED1_cntrl.vhd
set_global_assignment -name VHDL_FILE src/spi/tstcfg.vhd
set_global_assignment -name VHDL_FILE src/stream/stream_switch.vhd
set_global_assignment -name VHDL_FILE src/wfm_ram_buffer/wfm_wcmd_fsm.vhd
set_global_assignment -name VHDL_FILE src/wfm_ram_buffer/wfm_rcmd_fsm.vhd
set_global_assignment -name VHDL_FILE src/wfm_ram_buffer/wfm_player_top.vhd
set_global_assignment -name VHDL_FILE src/wfm_ram_buffer/wfm_player.vhd
set_global_assignment -name VHDL_FILE src/wfm_ram_buffer/wfm_pct_gen.vhd
set_global_assignment -name VHDL_FILE src/wfm_ram_buffer/pct_payload_extrct.vhd
set_global_assignment -name VHDL_FILE src/wfm_ram_buffer/DDR2_ctrl_top.vhd
set_global_assignment -name VHDL_FILE src/wfm_ram_buffer/DDR2_arb.vhd
set_global_assignment -name QIP_FILE ip/ddr2_traffic_gen/ddr2_traffic_gen/synthesis/ddr2_traffic_gen.qip
set_global_assignment -name VHDL_FILE src/revision/revision.vhd
set_global_assignment -name VHDL_FILE src/rx_path/wr_rx_fifo_v3.vhd
set_global_assignment -name VHDL_FILE src/rx_path/rx_pct_data_v2.vhd
set_global_assignment -name VHDL_FILE src/rx_path/rx_path.vhd
set_global_assignment -name VHDL_FILE src/rx_path/diq2_sampling.vhd
set_global_assignment -name VHDL_FILE src/rx_path/diq2_samples.vhd
set_global_assignment -name VHDL_FILE src/rx_path/compress_v2.vhd
set_global_assignment -name VHDL_FILE src/general/fifo_inst.vhd
set_global_assignment -name QXP_FILE "limesdr-pcie_xillybus_core/xillybus_core.qxp"
set_global_assignment -name VERILOG_FILE "limesdr-pcie_xillybus_core/xillybus.v"
set_global_assignment -name VHDL_FILE src/tx_packets/tx_pct_data_mimo_v3.vhd
set_global_assignment -name VHDL_FILE src/tx_modules/rd_tx_fifo.vhd
set_global_assignment -name VHDL_FILE src/tx_modules/lms7002_ddout.vhd
set_global_assignment -name VHDL_FILE src/reg_phase_shift/simple_reg.vhd
set_global_assignment -name VHDL_FILE src/reg_phase_shift/phase_shift.vhd
set_global_assignment -name VHDL_FILE src/pll_reconfig_ctrl/pll_reconfig_status.vhd
set_global_assignment -name VHDL_FILE src/general/my_sw.vhd
set_global_assignment -name BDF_FILE symbols/pll_block.bdf
set_global_assignment -name VHDL_FILE src/spi/pllcfg.vhd
set_global_assignment -name VHDL_FILE src/spi/fpgacfg.vhd
set_global_assignment -name QIP_FILE ip/pll_reconfig_module/pll_reconfig_module.qip
set_global_assignment -name VHDL_FILE src/nios_cpu/nios_cpu.vhd
set_global_assignment -name VHDL_FILE src/testing/pct_transfer_v2.vhd
set_global_assignment -name QIP_FILE software/lms_ctr_app/mem_init/meminit.qip
set_global_assignment -name VERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_uart.v -library lms_ctr
set_global_assignment -name VERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_sysid_qsys_0.v -library lms_ctr
set_global_assignment -name VERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_switch.v -library lms_ctr
set_global_assignment -name VERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_spi_lms.v -library lms_ctr
set_global_assignment -name VERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_oc_mem.v -library lms_ctr
set_global_assignment -name VERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_nios2_cpu_cpu_test_bench.v -library lms_ctr
set_global_assignment -name VERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_nios2_cpu_cpu_debug_slave_wrapper.v -library lms_ctr
set_global_assignment -name VERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_nios2_cpu_cpu_debug_slave_tck.v -library lms_ctr
set_global_assignment -name VERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_nios2_cpu_cpu_debug_slave_sysclk.v -library lms_ctr
set_global_assignment -name VERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_nios2_cpu_cpu.v -library lms_ctr
set_global_assignment -name VERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_nios2_cpu.v -library lms_ctr
set_global_assignment -name SYSTEMVERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_mm_interconnect_0_rsp_mux_001.sv -library lms_ctr
set_global_assignment -name SYSTEMVERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_mm_interconnect_0_rsp_mux.sv -library lms_ctr
set_global_assignment -name SYSTEMVERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_mm_interconnect_0_rsp_demux.sv -library lms_ctr
set_global_assignment -name SYSTEMVERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_mm_interconnect_0_router_004.sv -library lms_ctr
set_global_assignment -name SYSTEMVERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_mm_interconnect_0_router_002.sv -library lms_ctr
set_global_assignment -name SYSTEMVERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_mm_interconnect_0_router_001.sv -library lms_ctr
set_global_assignment -name SYSTEMVERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_mm_interconnect_0_router.sv -library lms_ctr
set_global_assignment -name SYSTEMVERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_mm_interconnect_0_cmd_mux_002.sv -library lms_ctr
set_global_assignment -name SYSTEMVERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_mm_interconnect_0_cmd_mux.sv -library lms_ctr
set_global_assignment -name SYSTEMVERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_mm_interconnect_0_cmd_demux_001.sv -library lms_ctr
set_global_assignment -name SYSTEMVERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_mm_interconnect_0_cmd_demux.sv -library lms_ctr
set_global_assignment -name SYSTEMVERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv -library lms_ctr
set_global_assignment -name VERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_mm_interconnect_0_avalon_st_adapter.v -library lms_ctr
set_global_assignment -name VERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_mm_interconnect_0.v -library lms_ctr
set_global_assignment -name VERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_lms_ctr_gpio.v -library lms_ctr
set_global_assignment -name VERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_leds.v -library lms_ctr
set_global_assignment -name SYSTEMVERILOG_FILE lms_ctr/synthesis/submodules/lms_ctr_irq_mapper.sv -library lms_ctr
set_global_assignment -name VHDL_FILE lms_ctr/synthesis/submodules/avfifo.vhd -library lms_ctr
set_global_assignment -name VERILOG_FILE lms_ctr/synthesis/submodules/altera_reset_synchronizer.v -library lms_ctr
set_global_assignment -name VERILOG_FILE lms_ctr/synthesis/submodules/altera_reset_controller.v -library lms_ctr
set_global_assignment -name SYSTEMVERILOG_FILE lms_ctr/synthesis/submodules/altera_merlin_slave_translator.sv -library lms_ctr
set_global_assignment -name SYSTEMVERILOG_FILE lms_ctr/synthesis/submodules/altera_merlin_slave_agent.sv -library lms_ctr
set_global_assignment -name SYSTEMVERILOG_FILE lms_ctr/synthesis/submodules/altera_merlin_master_translator.sv -library lms_ctr
set_global_assignment -name SYSTEMVERILOG_FILE lms_ctr/synthesis/submodules/altera_merlin_master_agent.sv -library lms_ctr
set_global_assignment -name SYSTEMVERILOG_FILE lms_ctr/synthesis/submodules/altera_merlin_burst_uncompressor.sv -library lms_ctr
set_global_assignment -name SYSTEMVERILOG_FILE lms_ctr/synthesis/submodules/altera_merlin_arbitrator.sv -library lms_ctr
set_global_assignment -name VERILOG_FILE lms_ctr/synthesis/submodules/altera_avalon_sc_fifo.v -library lms_ctr
set_global_assignment -name VHDL_FILE lms_ctr/synthesis/lms_ctr.vhd -library lms_ctr
set_global_assignment -name QIP_FILE ip/fifo_8b/fifo_8b.qip
set_global_assignment -name VERILOG_FILE ip/pcie_core/pcie_c4_4x_examples/chaining_dma/pcie_c4_4x_rs_hip.v
set_global_assignment -name VERILOG_FILE ip/pcie_core/pcie_c4_4x_serdes.v
set_global_assignment -name VERILOG_FILE "ip/pcie_core/ip_compiler_for_pci_express-library/altpcie_rs_serdes.v"
set_global_assignment -name VERILOG_FILE "ip/pcie_core/ip_compiler_for_pci_express-library/altpcie_reconfig_3cgx.v"
set_global_assignment -name VERILOG_FILE "ip/pcie_core/ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v"
set_global_assignment -name VHDL_FILE src/testing/pct_transfer.vhd
set_global_assignment -name VHDL_FILE src/data_manipulation/decompress.vhd
set_global_assignment -name VHDL_FILE src/tx_packets/tx_pct_data_mimo.vhd
set_global_assignment -name VHDL_FILE src/tx_packets/sample_nr_cnt_mimo.vhd
set_global_assignment -name VHDL_FILE src/testing/test_data.vhd
set_global_assignment -name VHDL_FILE src/pll_reconfig_ctrl/config_ctrl.vhd
set_global_assignment -name VHDL_FILE src/spi/miso_mux.vhd
set_global_assignment -name VHDL_FILE src/spi/txtspcfg.vhd
set_global_assignment -name VHDL_FILE src/spi/mem_package.vhd
set_global_assignment -name VHDL_FILE src/spi/mcfg32wm_fsm.vhd
set_global_assignment -name VHDL_FILE src/spi/mcfg_components.vhd
set_global_assignment -name VHDL_FILE src/general/alive.vhd
set_global_assignment -name VHDL_FILE src/general/debounce.vhd
set_global_assignment -name QIP_FILE ip/fpga_outfifo/fpga_outfifo.qip
set_global_assignment -name QIP_FILE ip/ddo/ddrox1.qip
set_global_assignment -name VHDL_FILE src/general/synchronizer.vhd
set_global_assignment -name VHDL_FILE src/general/capture_signal.vhd
set_global_assignment -name VHDL_FILE src/general/bus_synch.vhd
set_global_assignment -name BDF_FILE symbols/delay_chain.bdf
set_global_assignment -name BDF_FILE symbols/tx_synchronizers.bdf
set_global_assignment -name BDF_FILE symbols/LTE_rx_path.bdf
set_global_assignment -name BDF_FILE symbols/LTE_tx_path.bdf
set_global_assignment -name VHDL_FILE src/general/my_busmux.vhd
set_global_assignment -name VHDL_FILE src/pcie/pcie_top.vhd
set_global_assignment -name VHDL_FILE src/self_test/transition_count.vhd
set_global_assignment -name VHDL_FILE src/self_test/singl_clk_with_ref_test.vhd
set_global_assignment -name VHDL_FILE src/self_test/ddr2_tester.vhd
set_global_assignment -name VHDL_FILE src/self_test/clock_test.vhd
set_global_assignment -name VHDL_FILE src/self_test/clk_with_ref_test.vhd
set_global_assignment -name VHDL_FILE src/self_test/clk_no_ref_test.vhd
set_global_assignment -name VHDL_FILE src/general/onboard_led.vhd
set_global_assignment -name TCL_SCRIPT_FILE DDR2_2_pin_assigments.tcl
set_global_assignment -name VHDL_FILE src/rx_path_top/smpl_cnt/synth/smpl_cnt.vhd
set_global_assignment -name VHDL_FILE src/rx_path_top/diq2fifo/synth/test_data_dd.vhd
set_global_assignment -name VHDL_FILE src/rx_path_top/diq2fifo/synth/rxiq_siso_sdr.vhd
set_global_assignment -name VHDL_FILE src/rx_path_top/diq2fifo/synth/rxiq_siso_ddr.vhd
set_global_assignment -name VHDL_FILE src/rx_path_top/diq2fifo/synth/rxiq_siso.vhd
set_global_assignment -name VHDL_FILE src/rx_path_top/diq2fifo/synth/rxiq_pulse_ddr.vhd
set_global_assignment -name VHDL_FILE src/rx_path_top/diq2fifo/synth/rxiq_mimo_ddr.vhd
set_global_assignment -name VHDL_FILE src/rx_path_top/diq2fifo/synth/rxiq_mimo.vhd
set_global_assignment -name VHDL_FILE src/rx_path_top/diq2fifo/synth/rxiq.vhd
set_global_assignment -name VHDL_FILE src/rx_path_top/diq2fifo/synth/lms7002_ddin.vhd
set_global_assignment -name VHDL_FILE src/rx_path_top/diq2fifo/synth/diq2fifo.vhd
set_global_assignment -name VHDL_FILE src/rx_path_top/data2packets/synth/data2packets_top.vhd
set_global_assignment -name VHDL_FILE src/rx_path_top/data2packets/synth/data2packets_fsm.vhd
set_global_assignment -name VHDL_FILE src/rx_path_top/data2packets/synth/data2packets.vhd
set_global_assignment -name VHDL_FILE src/tx_path_top/fifo2diq/synth/txiq.vhd
set_global_assignment -name VHDL_FILE src/tx_path_top/fifo2diq/synth/fifo2diq.vhd
set_global_assignment -name VHDL_FILE src/tx_path_top/handshake_sync/synth/handshake_sync.vhd
set_global_assignment -name VHDL_FILE src/tx_path_top/tx_path/synth/tx_path_top.vhd
set_global_assignment -name VHDL_FILE src/tx_path_top/tx_path/synth/sync_fifo_rw.vhd
set_global_assignment -name VHDL_FILE src/general/gpio_ctrl_top.vhd
set_global_assignment -name VHDL_FILE src/general/gpio_ctrl.vhd
set_global_assignment -name SDC_FILE Clock_groups.sdc
set_global_assignment -name VHDL_FILE src/testing/rxiq_check.vhd
set_global_assignment -name VHDL_FILE src/testing/deinterleave_ch.vhd
set_global_assignment -name SMART_RECOMPILE OFF
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top