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codec_sve.txt
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codec_sve.txt
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# **********************************************************
# Copyright (c) 2016-2022 ARM Limited. All rights reserved.
# **********************************************************
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# * Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# * Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# * Neither the name of ARM Limited nor the names of its contributors may be
# used to endorse or promote products derived from this software without
# specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL ARM LIMITED OR CONTRIBUTORS BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
# DAMAGE.
# This file defines instruction encodings for the Scalable Vector Extension
# (SVE) and is a placeholder for future work. There are 1288 instructions in
# the specification including their variants. This file is for version 1 of
# SVE. Version 2 instructions will be defined in another codec_<version>.txt
# file when implemented.
# See header comments in codec_v80.txt and opnd_defs.txt to understand how
# instructions are defined for the purposes of decode and encode code
# generation.
# Instruction definitions:
00000100xx1xxxxx000000xxxxxxxxxx n 9 SVE add z0 : z5 z16 bhsd_sz
00000100xx011010000xxxxxxxxxxxxx n 21 SVE and z0 : p10_low z0 z5 bhsd_sz
00000100xx011011000xxxxxxxxxxxxx n 29 SVE bic z0 : p10_low z0 z5 bhsd_sz
00000100xx011001000xxxxxxxxxxxxx n 90 SVE eor z0 : p10_low z0 z5 bhsd_sz
00000100xx011000000xxxxxxxxxxxxx n 327 SVE orr z0 : p10_low z0 z5 bhsd_sz
00000100xx1xxxxx000100xxxxxxxxxx n 403 SVE sqadd z0 : z5 z16 bhsd_sz
00000100xx1xxxxx000110xxxxxxxxxx n 425 SVE sqsub z0 : z5 z16 bhsd_sz
00000100xx1xxxxx000001xxxxxxxxxx n 470 SVE sub z0 : z5 z16 bhsd_sz
00000100xx1xxxxx000101xxxxxxxxxx n 531 SVE uqadd z0 : z5 z16 bhsd_sz
00000100xx1xxxxx000111xxxxxxxxxx n 538 SVE uqsub z0 : z5 z16 bhsd_sz