Implement ARM64 [was: arm64: test "double_finalize" failed with panic 'not yet implemented']

[vielmetti]

System is an Ampere eMag, Packet c2.large.arm.

Build succeeds after applying the patch in bytecodealliance/cranelift#716 but a few tests fail.

test double_finalize ... FAILED

thread 'double_finalize' panicked at 'not yet implemented', cranelift-codegen/sr
c/isa/arm64/abi.rs:15:5

[vielmetti]

https://github.com/CraneStation/cranelift/blob/master/cranelift-codegen/src/isa/arm64/abi.rs clearly has a few "unimplemented" calls!

[bnjbvr]

Thanks for opening an issue. Unfortunately this happens because we don't have an aarch64 implementation yet, only stubs to have it compile. So Cranelift can't target the aarch64 architecture as of today. Would you be interested in helping adding support for it? (We're in the middle of rewriting the DSL that makes it easy to add new ISA targets, hopefully done in a few weeks/months, but work on this using the Python DSL could be done in the meanwhile)

[vielmetti]

Thanks @bnjbvr - glad that you've done the work to make it compile with stubs, that will make this work easier. I am talking to a bunch of aarch64 folks next week, and will bring up the question. Do you have any sense of degree of difficulty to do this work? (e.g. how much familiarity with the instruction set is required)

[bnjbvr]

One should know how to encode ARM64 instructions (or read the ARM ARM), and some other low-level details which are a bit hard to enumerate. For instance, something that comes to mind is that ARM/aarch64 have restrictions in ranges of jump targets, but this should already be gracefully handled by Cranelift. Another example is that there are many ways to emit immediates bigger than an instruction's size with aarch64, and some of them are more optimized than others. My guts would tell me that implementing something that works would be a great first step, and that implementing something very optimized could wait a bit.

See this (quite stall, very wip-y) commit from a stall branch that implemented a simple aarch64 move, this can give hints about where to read / start etc..

[cfallin]

As a note to link this with current efforts, we are developing an ARM4 backend as part of the new instruction selector rework (#1344). This will hopefully fall into place within the next few months.

[cfallin]

Fixed with #1494.