Tutorials/labTemplateFolder/lab_template.ipynb

{
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   "source": [
    "## **Instructions**\n",
    "This lab was created to act as a template that can be copied and edited in order to create new lab exercises or allow for experimentation and updates to current labs. \n",
    "There are seven major tools that are seen throughout the labs. They are listed below along with their common usage, that can all be easily incorporated into your lab creation. "
   ]
  },
  {
   "cell_type": "markdown",
   "id": "f097a78f",
   "metadata": {},
   "source": [
    "## **Tools and their descriptions and how they are used**\n",
    "\n",
    "VCD (Value Change Dump):\n",
    "- VCD is a file format used to record changes in electrical signals over time.\n",
    "- It's used to analyze how signals in an electronic system change and interact over time, helping engineers understand the behavior of their designs.\n",
    "\n",
    "Wavedrom:\n",
    "- WaveDrom is a tool that creates visual diagrams of electronic signals, known as waveforms, from a textual description.\n",
    "- It helps in visualizing how signals in an electronic system change over time, making it easier for people to understand complex interactions between different parts of the system. \n",
    "- Generates waveforms from a .vcd file\n",
    "\n",
    "Verilator:\n",
    "- Verilator is a software tool that converts Verilog code (a language used to describe electronic systems) into a program in C++ or SystemC. This program is used to simulate the behavior of the electronic system described by the Verilog code.\n",
    "- It allows engineers to test and verify their electronic designs on a computer before building a physical prototype.\n",
    "\n",
    "Simulation Workspace:\n",
    "- A simulation workspace is a virtual environment where engineers and designers can test and analyze their electronic or digital designs.\n",
    "- It provides a controlled setting where various scenarios and conditions can be simulated to see how a design behaves, helping identify and fix issues before creating a real product.\n",
    "These tools are typically used hand in hand, as they all relate to each other. \n",
    "\n",
    "XDC File Generation:\n",
    "- XDC stands for Xilinx Design Constraints. The master XDC file has each of the ports for input and output on the Basys3 board. The XDC file connects signals with physical hardware. This will be needed to bind signals to switches, LEDs and buttons.\n",
    "- Uncomment the lines containing btnr, btnl, btnu, and btnd. This tells the FPGA what input is linked to button.\n",
    "- NOTE: In future labs, if you're clever about how you name your signals in your top level module, you won't need to rename any signals in the .xdc but will just uncomment the lines that you need.\n",
    "You will need to uncomment the lines that contain the button signals. The lines look like this:\n",
    "set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { btnc }];\n",
    "- Then run the codeblock to save your constraints file.\n",
    "\n",
    "F4PGA Toolchain:\n",
    "- This toolchain in particular focuses on converting hardware code into a design that can be more easily implemented onto an FPGA. \n",
    "- It creates a binary file that can be loaded onto an FPGA to configure it to work as desired. \n",
    "- More of a troubleshooting and testing the code that you used, requires the generation of an XDC file first.\n",
    "\n",
    "OpenOCD (Open On-Chip Debugger):\n",
    "- Open-source software used to help debug embedded systems in real time\n",
    "- Allows for programming and reprogramming of microcontrollers and the like directly in the circuit instead of needing to replace or remove them.\n",
    "\n",
    "These are just a quick tidbit of the usage of each of these tools, for more information refer to how they are used in other labs or researching online common usages.\n",
    "\n",
    "NOTE: You may need to verify that the filepaths are update for your usage so that each tool works properly. "
   ]
  },
  {
   "cell_type": "markdown",
   "id": "ace1ff52",
   "metadata": {},
   "source": [
    "# Lab Title\n",
    "Briefly introduce the lab, including its objectives and what the student will learn or achieve by completing it."
   ]
  },
  {
   "cell_type": "markdown",
   "id": "6d15efc2",
   "metadata": {},
   "source": [
    "## **Setup**\n",
    "Provide detailed instructions on how to set up the environment for the lab. This may include installing software, setting up hardware, or preparing any necessary files or dependencies.\n",
    "The following cells is run, with the generic setup for the majority of labs. The Wavedrom Extension is not used as much, but can be used for specific instances.\n",
    "The Setup cell is commented with various information, that can be adapted for usage"
   ]
  },
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   "outputs": [],
   "source": [
    "#@title Install VCD\n",
    "!git clone https://github.com/yne/vcd.git\n",
    "!make -C /content/vcd\n",
    "%cd /content/vcd\n",
    "!make install\n",
    "%cd /"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "id": "2e6f6bbd",
   "metadata": {
    "vscode": {
     "languageId": "plaintext"
    }
   },
   "outputs": [],
   "source": [
    "#@title Import Files from Repo\n",
    "import ipywidgets as widgets\n",
    "from ipywidgets import GridspecLayout\n",
    "from ipywidgets import AppLayout, Button, Layout, jslink, IntText, IntSlider\n",
    "import requests\n",
    "\n",
    "!mkdir -p /content/tmp_code\n",
    "#Creates a text document using the Raw github url. This text document will be used as a .py file for imports\n",
    "def import_text(text):\n",
    "  url = \"https://raw.githubusercontent.com/byuccl/digital_design_colab/master/Labs/arithmetic_lab/files/%s\" % text\n",
    "  resp = requests.get(url)\n",
    "  with open(text, 'wb') as f:\n",
    "    f.write(resp.content)\n",
    "\n",
    "import_text(\"import_all.py\")\n",
    "from import_all import *\n",
    "import_source()\n",
    "import_packages()\n",
    "from simulation import *\n",
    "from vcd2wd import *"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "id": "62ad3a0c",
   "metadata": {
    "vscode": {
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    }
   },
   "outputs": [],
   "source": [
    "#@title Install Verilator\n",
    "!apt-get install verilator >/dev/null"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "id": "a60338d8",
   "metadata": {
    "vscode": {
     "languageId": "plaintext"
    }
   },
   "outputs": [],
   "source": [
    "#@title Install Wavedrom Extension\n",
    "!pip install --upgrade git+https://github.com/anon36424/nb_js_diagrammers.git\n",
    "%load_ext nb_js_diagrammers"
   ]
  },
  {
   "cell_type": "markdown",
   "id": "6ed04607",
   "metadata": {},
   "source": [
    "## Introduction\n",
    "Introduce the main concepts and background information necessary to understand and complete the lab. This section should provide a solid foundation for the tasks that will be performed."
   ]
  },
  {
   "cell_type": "markdown",
   "id": "b88e63c4",
   "metadata": {},
   "source": [
    "## Common Tools\n",
    "The cells below outline a lot of the common tools and their usage throughout labs"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "id": "7ca7ea13",
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   "source": [
    "#@title Launch Simulation Workspace \n",
    "NOTE: You MUST run the simulation before the tools below will work properly, as it is this generation that allows the visualization of the wavedrom. \n",
    "createSimulationWorkSpace(\"tmp_code/full_add\")"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "id": "569b4201",
   "metadata": {
    "vscode": {
     "languageId": "plaintext"
    }
   },
   "outputs": [],
   "source": [
    "#@title Verilator TestBench\n",
    "# !verilator --cc full_add \n",
    "!verilator -Wall --trace -cc full_add.sv --exe tb_full_add.cpp\n",
    "!make -C obj_dir -f Vfull_add.mk Vfull_add > /dev/null\n",
    "!./obj_dir/Vfull_add"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "id": "77f8de86",
   "metadata": {
    "vscode": {
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    }
   },
   "outputs": [],
   "source": [
    "#@title Create WaveDrom\n",
    "df2wd(\"full_add\")"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "id": "f5e50789",
   "metadata": {
    "vscode": {
     "languageId": "plaintext"
    }
   },
   "outputs": [],
   "source": [
    "#@title Show WaveDrom\n",
    "%%wavedrom_magic -h 200 -o /content/tmp_code/full_add.txt\n",
    "---"
   ]
  },
  {
   "cell_type": "markdown",
   "id": "ed016405",
   "metadata": {},
   "source": [
    "## Objectives\n",
    "List the specific objectives or tasks that the student will accomplish in this lab. Objectives should be clear, measurable, and directly related to the learning goals of the lab."
   ]
  },
  {
   "cell_type": "markdown",
   "id": "afe2ed92",
   "metadata": {},
   "source": [
    "### Objective 1: [Title]\n",
    "- Description: Briefly describe what the student will do in this objective.\n",
    "- Steps: Outline the steps the student will follow to complete the objective.\n",
    "- Expected Outcome: Describe what success looks like for this objective."
   ]
  },
  {
   "cell_type": "markdown",
   "id": "b8347f4e",
   "metadata": {},
   "source": [
    "## Additional Concepts\n",
    "If there are additional concepts or advanced topics that the student will encounter, provide explanations or references here. This section can be used to deepen understanding or to introduce related topics that enhance the lab experience. You could also potentially reference types of questions to cement understanding, such as the ones used in the lessons. If you want to incorporate that here, utilize the create lesson template and add that here. "
   ]
  },
  {
   "cell_type": "markdown",
   "id": "81687aee",
   "metadata": {},
   "source": [
    "## Conclusion\n",
    "Summarize what the student has learned and accomplished in the lab. Discuss how the skills or knowledge gained can be applied in other scenarios or future projects."
   ]
  },
  {
   "cell_type": "markdown",
   "id": "4686d20c",
   "metadata": {},
   "source": [
    "## Challenges (Optional)\n",
    "Provide optional challenges or extension activities for students who finish early or wish to explore further. These should build on the lab's content and encourage deeper engagement with the material."
   ]
  },
  {
   "cell_type": "markdown",
   "id": "d0c041d5",
   "metadata": {},
   "source": [
    "# **Usage of F4PGA Toolchain and relating tools**\n",
    "\n",
    "At the end of the lab is typically where toolchain is run, to allow for the connection of signals to physical hardware. Below are the tools used to do this that can be incorporated into your own lab. "
   ]
  },
  {
   "cell_type": "markdown",
   "id": "c657a8a8",
   "metadata": {},
   "source": [
    "#### ***XDC Files:***"
   ]
  },
  {
   "cell_type": "markdown",
   "id": "a376aead",
   "metadata": {},
   "source": [
    "\n",
    "XDC stands for Xilinx Design Constraints. The master XDC file  has each of the ports for input and output on the Basys3 board. The XDC file connects signals with physical hardware. This will be needed to bind signals to switches, LEDs and buttons. \n",
    "\n",
    "Uncomment the lines containing `btnr`, `btnl`, `btnu`, and `btnd`. This tells the FPGA what input is linked to button.\n",
    "\n",
    "***NOTE***: In future labs, if you're clever about how you name your signals in your top level module, you won't need to rename any signals in the .xdc but will just uncomment the lines that you need.\n",
    "\n",
    "You will need to uncomment the lines that contain the button signals.\n",
    "The lines look like this:  \n",
    "`# set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { btnc }];`\n",
    "\n",
    "Then run the codeblock to save your constraints file."
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "id": "b27592f0",
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   "source": [
    "#@title Generate an XDC File\n",
    "%%bash -c 'cat > /content/tmp_code/xdc.xdc'\n",
    "\n",
    "## Buttons\n",
    "# set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { btnc }];\n",
    "set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { btnu }];\n",
    "set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { btnl }];\n",
    "set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports { btnr }];\n",
    "set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { btnd }];\n",
    "\n",
    "## Switches\n",
    "set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { sw[0] }];\n",
    "set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }];\n",
    "set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }];\n",
    "set_property -dict { PACKAGE_PIN W17   IOSTANDARD LVCMOS33 } [get_ports { sw[3] }];\n",
    "set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports { sw[4] }];\n",
    "set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { sw[5] }];\n",
    "set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports { sw[6] }];\n",
    "set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { sw[7] }];\n",
    "set_property -dict { PACKAGE_PIN V2    IOSTANDARD LVCMOS33 } [get_ports { sw[8] }];\n",
    "set_property -dict { PACKAGE_PIN T3    IOSTANDARD LVCMOS33 } [get_ports { sw[9] }];\n",
    "set_property -dict { PACKAGE_PIN T2    IOSTANDARD LVCMOS33 } [get_ports { sw[10] }];\n",
    "set_property -dict { PACKAGE_PIN R3    IOSTANDARD LVCMOS33 } [get_ports { sw[11] }];\n",
    "set_property -dict { PACKAGE_PIN W2    IOSTANDARD LVCMOS33 } [get_ports { sw[12] }];\n",
    "set_property -dict { PACKAGE_PIN U1    IOSTANDARD LVCMOS33 } [get_ports { sw[13] }];\n",
    "set_property -dict { PACKAGE_PIN T1    IOSTANDARD LVCMOS33 } [get_ports { sw[14] }];\n",
    "set_property -dict { PACKAGE_PIN R2    IOSTANDARD LVCMOS33 } [get_ports { sw[15] }];\n",
    "\n",
    "## LEDs\n",
    "set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { led[0] }];\n",
    "set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports { led[1] }];\n",
    "set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { led[2] }];\n",
    "set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports { led[3] }];\n",
    "set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { led[4] }];\n",
    "set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { led[5] }];\n",
    "set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { led[6] }];\n",
    "set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { led[7] }];\n",
    "set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { led[8] }];\n",
    "set_property -dict { PACKAGE_PIN V3    IOSTANDARD LVCMOS33 } [get_ports { led[9] }];\n",
    "set_property -dict { PACKAGE_PIN W3    IOSTANDARD LVCMOS33 } [get_ports { led[10] }];\n",
    "set_property -dict { PACKAGE_PIN U3    IOSTANDARD LVCMOS33 } [get_ports { led[11] }];\n",
    "set_property -dict { PACKAGE_PIN P3    IOSTANDARD LVCMOS33 } [get_ports { led[12] }];\n",
    "set_property -dict { PACKAGE_PIN N3    IOSTANDARD LVCMOS33 } [get_ports { led[13] }];\n",
    "set_property -dict { PACKAGE_PIN P1    IOSTANDARD LVCMOS33 } [get_ports { led[14] }];\n",
    "set_property -dict { PACKAGE_PIN L1    IOSTANDARD LVCMOS33 } [get_ports { led[15] }];"
   ]
  },
  {
   "cell_type": "markdown",
   "id": "29b79f43",
   "metadata": {},
   "source": [
    "\n",
    "## **Compiling with the F4PGA Toolchain**"
   ]
  },
  {
   "cell_type": "markdown",
   "id": "c2434608",
   "metadata": {},
   "source": [
    "### Installing the Toolchain\n",
    "\n",
    "Click play. This may take up to 4 minutes."
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "id": "757f1b16",
   "metadata": {
    "vscode": {
     "languageId": "plaintext"
    }
   },
   "outputs": [],
   "source": [
    "!apt install -y git wget xz-utils"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "id": "eb4a8336",
   "metadata": {
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   },
   "outputs": [],
   "source": [
    "%%bash\n",
    "cd /content\n",
    "git clone https://github.com/chipsalliance/f4pga-examples\n",
    "cd /content/f4pga-examples\n",
    "time wget https://repo.continuum.io/miniconda/Miniconda3-latest-Linux-x86_64.sh -O conda_installer.sh\n"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "id": "fe81b3d6",
   "metadata": {
    "vscode": {
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    }
   },
   "outputs": [],
   "source": [
    "#Creates the Conda Environment\n",
    "%%bash\n",
    "cd /content/f4pga-examples\n",
    "export F4PGA_INSTALL_DIR=~/opt/f4pga\n",
    "export FPGA_FAM=xc7\n",
    "time bash conda_installer.sh -u -b -p $F4PGA_INSTALL_DIR/$FPGA_FAM/conda;\n",
    "time source \"$F4PGA_INSTALL_DIR/$FPGA_FAM/conda/etc/profile.d/conda.sh\";\n",
    "time conda env create -f $FPGA_FAM/environment.yml"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "id": "2d1dfccd",
   "metadata": {
    "vscode": {
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    }
   },
   "outputs": [],
   "source": [
    "#Download F4PGA Arch Defs\n",
    "%%bash\n",
    "export F4PGA_INSTALL_DIR=~/opt/f4pga\n",
    "export FPGA_FAM=xc7\n",
    "source \"$F4PGA_INSTALL_DIR/$FPGA_FAM/conda/etc/profile.d/conda.sh\";\n",
    "conda activate xc7\n",
    "mkdir -p $F4PGA_INSTALL_DIR/xc7/install\n",
    "\n",
    "F4PGA_TIMESTAMP='20220920-124259'\n",
    "F4PGA_HASH='007d1c1'\n",
    "export F4PGA_PACKAGES='install-xc7 xc7a50t_test'\n",
    "\n",
    "for PKG in $F4PGA_PACKAGES; do\n",
    "  wget -qO- https://storage.googleapis.com/symbiflow-arch-defs/artifacts/prod/foss-fpga-tools/symbiflow-arch-defs/continuous/install/${F4PGA_TIMESTAMP}/symbiflow-arch-defs-${PKG}-${F4PGA_HASH}.tar.xz | tar -xJC $F4PGA_INSTALL_DIR/${FPGA_FAM}\n",
    "done"
   ]
  },
  {
   "cell_type": "markdown",
   "id": "52f48db6",
   "metadata": {},
   "source": [
    "### Compiling the Lab with the Toolchain\n",
    "This should take up to 3 minutes"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "id": "1247415f",
   "metadata": {
    "vscode": {
     "languageId": "plaintext"
    }
   },
   "outputs": [],
   "source": [
    "#This creates the Makefile\n",
    "with open(\"/content/tmp_code/Makefile\", \"w\") as f:\n",
    "  f.write(\"\"\"current_dir := ${CURDIR}\n",
    "TARGET := basys3\n",
    "\n",
    "TOP := dataflow_sv\n",
    "\n",
    "XDC := ${current_dir}/*.xdc\n",
    "\n",
    "SOURCES := ${current_dir}/dataflow.sv\n",
    "\n",
    "include /content/f4pga-examples/common/common.mk\n",
    "\"\"\")"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "id": "a623cc31",
   "metadata": {
    "vscode": {
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   },
   "outputs": [],
   "source": [
    "#Make the project\n",
    "%%bash\n",
    "export F4PGA_INSTALL_DIR=~/opt/f4pga\n",
    "export FPGA_FAM=xc7\n",
    "export TARGET=basys3\n",
    "export FOLDER=Dataflow_SV\n",
    "export FILES=\"Makefile xdc.xdc dataflow.sv\"\n",
    "source \"$F4PGA_INSTALL_DIR/$FPGA_FAM/conda/etc/profile.d/conda.sh\";\n",
    "mkdir -p /content/\"$FOLDER\"\n",
    "cd /content/tmp_code\n",
    "for file in $FILES\n",
    "do \n",
    "    cp \"$file\" /content/\"$FOLDER\"/\n",
    "done\n",
    "conda activate xc7\n",
    "cd /content/$FOLDER\n",
    "cp /content/tmp_code/errorFeedback.py ./\n",
    "time SURELOG_CMD=\"-parse\" make 2> ./error.txt 1>./compile.txt\n",
    "python errorFeedback.py"
   ]
  },
  {
   "cell_type": "markdown",
   "id": "0d328f69",
   "metadata": {},
   "source": [
    "## **Testing it on the board**\n",
    "\n",
    "To Download it to the board you will need OpenOCD.  \n",
    "\n",
    "First create a folder to house the files on your local machine. Then download the OpenOCD configure file and the bitstream from this Notebook and add then to your folder (they will be in a zip file in /content/dataflow_sv.zip). On command line go into the folder and run the command   \n",
    "\n",
    "`openocd --file Dataflow_SV.cfg`\n",
    "\n",
    "It should only take a few moments to download to the board."
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "id": "c6e597cb",
   "metadata": {
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   "outputs": [],
   "source": [
    "#@title Create File for openocd\n",
    "folder = \"Dataflow_SV\"\n",
    "\n",
    "with open(f\"/content/{folder}.cfg\", \"w\") as f:\n",
    "  f.write(\"\"\"interface ftdi\n",
    "ftdi_device_desc \"Digilent USB Device\"\n",
    "ftdi_vid_pid 0x0403 0x6010\n",
    "# channel 1 does not have any functionality\n",
    "ftdi_channel 0\n",
    "# just TCK TDI TDO TMS, no reset\n",
    "ftdi_layout_init 0x0088 0x008b\n",
    "reset_config none\n",
    "adapter_khz 10000\n",
    "\n",
    "source [find cpld/xilinx-xc7.cfg]\n",
    "source [find cpld/jtagspi.cfg]\n",
    "init\n",
    "\n",
    "puts [irscan xc7.tap 0x09]\n",
    "\n",
    "set xc7a35t \"0362D093\"\n",
    "set xc7a100t \"13631093\"\n",
    "set code [drscan xc7.tap 32 0]  \n",
    "puts $code\n",
    "\n",
    "if { $code == $xc7a35t} {\n",
    "    puts \"The board has an xc7a35t\"\n",
    "}\n",
    "\n",
    "if { $code == $xc7a100t} {\n",
    "    puts \"The board has an xc7a100t\"\n",
    "}\n",
    "\"\"\"\n",
    "+\n",
    "f\"\"\"\n",
    "puts \"Programming...\"\n",
    "pld load 0 {folder}.bit\n",
    "exit\"\"\"\n",
    ")"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "id": "07efb526",
   "metadata": {
    "vscode": {
     "languageId": "plaintext"
    }
   },
   "outputs": [],
   "source": [
    "#@title Create Zip\n",
    "%%bash\n",
    "cd /content\n",
    "export FOLDER=Dataflow_SV\n",
    "cp $FOLDER/build/basys3/*.bit ./\n",
    "zip $FOLDER.zip *.bit $FOLDER.cfg\n"
   ]
  },
  {
   "cell_type": "markdown",
   "id": "aee1ea88",
   "metadata": {},
   "source": [
    "## References\n",
    "List any references, resources, or further reading that can help students understand the lab's topics in more depth.\n",
    "This is also where you would typically link the next lesson, lab, or tutorial"
   ]
  }
 ],
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