[fud] xclbin stage should use Xilinx paths, etc., from the configuration rather than hard-coding them

[andrewb1999]

In xclbin.py the locations of vivado and v++ are hard-coded instead of being based on some value in the configuration file. This prevents the xclbin stage from working on computers where vivado is installed in a different location. If someone can let me know of the proper way to fix this issue I'll submit a pull request with the changes.

[rachitnigam]

The jq stage might be a good example for how to do this: https://github.com/cucapra/calyx/blob/master/fud/fud/stages/jq.py#L24

Essentially, you get access to the config field in _define_steps where you can get the value of a configuration variable and use it. The hardcoding in xclbin.py happens here: https://github.com/cucapra/calyx/blob/master/fud/fud/stages/xilinx/xclbin.py#L98

We can replace it with self.config["stages", self.name, "exec"]. Out of curiousity, what are you using this for? @nathanielnrn is working on making emulation.py the default way to synthesize things through Vivado and might be worth coordinating with.

[andrewb1999]

Yeah I realized after I wrote this that there is still ongoing work to get Calyx running on xilinx fpgas. I eventually want to run on real FPGAs, but I can pause this for now while development work is still ongoing.

[andrewb1999]

Closing for now while the xilinx flow is still in development, will reopen if it is still relevant in the future.

[sampsyo]

Yo! Yes, this is indeed a problem! The overall issue is actually tracked in #856. The configuration of all this stuff is a total mess; some places it's hard-coded, and some places it's configured redundantly across multiple different stages' isolated configurations; etc.

If you're cool with it, I'll actually reopen this in order to track the very specific/near-term problem of adding configuration options to the xclbin stage… we should absolutely do that before completely solving #856 by rethinking/collapsing all the various messy options into one set as that issue suggests.

Perhaps an even more pertinent example of what needs to be done here is in the analogous configuration in the vestigial emulation stage:
https://github.com/cucapra/calyx/blob/fcbd6bcc5201b07de6dde534f1c4af9d0bb35457/fud/fud/stages/xilinx/emulation.py#L39