First-class combinational components

[sampsyo]

Calyx supports comb groups (introduced in #635) for encapsulating combinational (sub-cycle) logic, and primitive components (ones implemented externally in RTL) are allowed to be declared as combinational. The standard library relies heavily on these primitives—for example, std_add is a combinational primitive.

However, Calyx-implemented component definitions must take at least one cycle. (As a side note, it would be great to document this fact, even before we change it…) As an aspiration, it would be great to be able to implement combinational components in Calyx so you are not forced to switch to Verilog if you want to build up combinational abstractions. For example, you might like to implement an add3 component that uses two std_adds to add together 3 inputs instead of 2.

Some open questions here include:

• Can these components have a non-empty control program? (Probably not, at least in the first version. Our control statements are sequential by nature.)
• How do we enforce combinational-ness? (You can only instantiate combinational subcomponents, maybe?) Or do we just assume it?
• Are there any complexities in the compilation process that are not present for combinational primitives?

As background, this came up most recently in #1050 (reply in thread), i.e., in the context of the resource sharing pass (and inferring shareability). We previously implemented combinational groups and primitives in #635. This is also related to the discussions in #788 about how you're allowed to use done, when we sort of figured out that we wanted all components to be sequential in that their done condition is held by a register.

[andrewb1999]

Bumping this as it would significantly simplify code generation for the memory compiler. @matth2k or I might try to tackle this soon.