Change well-formedness check to allow for toplevel ref
memories
#1933
Labels
C: FPGA
Changes for the FPGA backend
ref
memories
#1933
As part of #1932 and #1733 we probably want to allow toplevel modules to contain
ref
memories and still be considered wellformed. Perhaps only if we designate that we wish to compile for synthesis/AXI wrapped. Not sure where this well-formed check lives as of writing.The text was updated successfully, but these errors were encountered: