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Change well-formedness check to allow for toplevel ref memories #1933

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nathanielnrn opened this issue Feb 24, 2024 · 2 comments
Closed

Change well-formedness check to allow for toplevel ref memories #1933

nathanielnrn opened this issue Feb 24, 2024 · 2 comments
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C: FPGA Changes for the FPGA backend

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@nathanielnrn
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As part of #1932 and #1733 we probably want to allow toplevel modules to contain ref memories and still be considered wellformed. Perhaps only if we designate that we wish to compile for synthesis/AXI wrapped. Not sure where this well-formed check lives as of writing.

@sampsyo
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sampsyo commented Feb 27, 2024

The check lives here!

// Main component cannot use `ref` cells
if comp.name == ctx.entrypoint {
for cell in comp.cells.iter() {
if cell.borrow().is_reference() {
return Err(Error::malformed_structure(
"ref cells are not allowed for main component",
)
.with_pos(cell.borrow().get_attributes()));
}
}
}

I say we can just delete this. No fuss, no muss.

@nathanielnrn
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Closed via #1952

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Labels
C: FPGA Changes for the FPGA backend
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