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Make calyx-py AXI wrapper cocotb testbench accept yxi interfaces and dynamic input data #1938

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nathanielnrn opened this issue Feb 28, 2024 · 0 comments · Fixed by #1997
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C: FPGA Changes for the FPGA backend

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@nathanielnrn
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Currently, the tests in axi-combined-calyx.py use hardcoded memory names and parameters for a simple vec_add kernel. To generalize the infrastructure for creating new tests for it would make sense to parameterize some of these tests off of .yxi interfaces.

We could also imagine passing in input data and using runt to check for output data, as opposed to the assertions that we currently have in axi-combined-calyx.py. This would likely look very similar to the Xilinx cocotb testbench testbench, and perhaps that python program could be refactored to work for both Xilinx/verilog wrapper tests and our current calyx-axi tests.

@nathanielnrn nathanielnrn added the C: FPGA Changes for the FPGA backend label Feb 28, 2024
@nathanielnrn nathanielnrn changed the title Improve calyx-py AXI wrapper cocotb testbench to accept yxi interfaces and dynamic input Make calyx-py AXI wrapper cocotb testbench accept yxi interfaces and dynamic input data Feb 28, 2024
@nathanielnrn nathanielnrn linked a pull request May 4, 2024 that will close this issue
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