Make calyx-py
AXI wrapper cocotb
testbench accept yxi
interfaces and dynamic input data
#1938
Labels
C: FPGA
Changes for the FPGA backend
calyx-py
AXI wrapper cocotb
testbench accept yxi
interfaces and dynamic input data
#1938
Currently, the tests in
axi-combined-calyx.py
use hardcoded memory names and parameters for a simplevec_add
kernel. To generalize the infrastructure for creating new tests for it would make sense to parameterize some of these tests off of.yxi
interfaces.We could also imagine passing in input data and using
runt
to check for output data, as opposed to the assertions that we currently have inaxi-combined-calyx.py
. This would likely look very similar to the Xilinx cocotb testbench testbench, and perhaps that python program could be refactored to work for both Xilinx/verilog wrapper tests and our current calyx-axi tests.The text was updated successfully, but these errors were encountered: