[fud] Revamp Xilinx fpga
stage to work for both emulation and execution
#872
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fpga
stage to work for both emulation and execution
#872
As it stands, there are two fud stages available to run Xilinx
xclbin
-compiled bitstreams:emulation.py
, there is a stage that uses a host C++ source file to run the whole shebang. This requires you to write the C++ testbench yourself and provide it as a configuration option. This is what I have documented so far in thexilinx.md
chapter (only because it was the first one I've tried).execution.py
, there's a very different approach in thefpga
stage: it imports PyOpenCL and uses that to load up and invoke the kernel directly. So there is no host C++ program; thefud
Python process itself talks to the device.As the names imply, I think @sgpthomas originally meant for these two stages to cover emulation & actual FPGA execution, respectively. But I have ben able to get the
fpga
stage to do emulation (in short, XRT respects the environment variable settingXCL_EMULATION_MODE=hw_emu
and does emulation).So my proposal here is to remove the
emulation.py
route and replace it with a spruced-up version of thefpga
stage. Specifically, the plan would be this:fud
) tool for runningxclbin
files. Thefud
stage would then run this tool as a subprocess. This tool would take care of loading up the data file, loading thexclbin
, invoking it, and collecting the results. Although it seems odd, there are several reasons to propose a standalone tool:xclbin
files without using fud.fud
do the dirty work of setting up the environment before invoking the tool (e.g., by sourcing the XRT setup script). This way, fud users would not need to bother with this nonsense themselves, as they currently do.xrt.ini
file for configuration and instead usexrt::ini::set
directly.The text was updated successfully, but these errors were encountered: