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Disallow @external in subcomponents when generating verilog #987

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rachitnigam opened this issue Apr 25, 2022 · 0 comments · Fixed by #1043
Closed

Disallow @external in subcomponents when generating verilog #987

rachitnigam opened this issue Apr 25, 2022 · 0 comments · Fixed by #1043
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C: Calyx Extension or change to the Calyx IL Type: Bug Bug in the implementation

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@rachitnigam
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The code generator will generate incorrect code if it sees @external in sub-components. When code generating Verilog, only the main module should have @external.
@rachitnigam rachitnigam added Type: Bug Bug in the implementation C: Calyx Extension or change to the Calyx IL labels Apr 25, 2022
@rachitnigam rachitnigam mentioned this issue May 5, 2022
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@rachitnigam rachitnigam mentioned this issue Jun 18, 2022
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C: Calyx Extension or change to the Calyx IL Type: Bug Bug in the implementation
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Disallow @external outside main calyxir/calyx
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@rachitnigam