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A mapping for PWM phandles needs to be defined in the sixtron_connector.dtsi in order to be easily used for pwm specifiers.
zephyr_zest-core-nrf5340/boards/catie/zest_core_nrf5340/sixtron_connector.dtsi
Line 48 in 7a861d1
<DIO18 0 &gpio1 11 0>; + + sixtron_connector_1_pwm: sixtron-connector-1-pwm { + compatible = "sixtron-pwm"; + #pwm-cells = <3>; + pwm-map-mask = <0xffffffff 0x0 0x0>; + pwm-map-pass-thru = <0x0 0xffffffff 0x0f>; + pwm-map = <PWM1 0 0 &<PERIPHERAL> <CHANNEL> 0 0>, + <PWM2 0 0 &<PERIPHERAL> <CHANNEL> 0 0>, + <PWM3 0 0 &<PERIPHERAL> <CHANNEL> 0 0>; + }
An example to populate PERIPHERAL and CHANNEL is available here:
pwm-map = <PWM1 0 0 &pwm1 3 0 0>, <PWM2 0 0 &pwm1 2 0 0>, <PWM3 0 0 &pwm3 3 0 0>;
A label needs to defines the default pwm nexus.
Line 58 in 7a861d1
sixtron_spi: &sixtron_connector_1_spi {}; + sixtron_pwm: &sixtron_connector_1_pwm {};
Caution
Be sure to compile example to validate the nexus.
The text was updated successfully, but these errors were encountered:
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A mapping for PWM phandles needs to be defined in the sixtron_connector.dtsi in order to be easily used for pwm specifiers.
zephyr_zest-core-nrf5340/boards/catie/zest_core_nrf5340/sixtron_connector.dtsi
Line 48 in 7a861d1
An example to populate PERIPHERAL and CHANNEL is available here:
A label needs to defines the default pwm nexus.
zephyr_zest-core-nrf5340/boards/catie/zest_core_nrf5340/sixtron_connector.dtsi
Line 58 in 7a861d1
sixtron_spi: &sixtron_connector_1_spi {}; + sixtron_pwm: &sixtron_connector_1_pwm {};
Caution
Be sure to compile example to validate the nexus.
The text was updated successfully, but these errors were encountered: