-
Notifications
You must be signed in to change notification settings - Fork 3
/
lagtester.qsf
205 lines (190 loc) · 10.8 KB
/
lagtester.qsf
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 02:13:21 January 18, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# lagtester_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M02SCE144C8G
set_global_assignment -name TOP_LEVEL_ENTITY lagtester
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "02:13:21 JANUARY 18, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "50.0 %"
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name NUM_PARALLEL_PROCESSORS 2
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
########################################################
# timing optimization
########################################################
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
#set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 16.0
#set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 8.0
#set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
#set_global_assignment -name FITTER_EFFORT "AUTO FIT"
#set_global_assignment -name SEED 12
#set_global_assignment -name AUTO_RAM_RECOGNITION Off
#set_global_assignment -name AUTO_ROM_RECOGNITION Off
########################################################
# source files
########################################################
set_global_assignment -name SDC_FILE lagtester.sdc
set_global_assignment -name VERILOG_FILE source/lagtester.v
set_global_assignment -name QIP_FILE source/pll/pll.qip
set_global_assignment -name QIP_FILE source/pll/pll_reconf.qip
set_global_assignment -name QIP_FILE source/misc/data_fifo.qip
set_global_assignment -name VERILOG_FILE source/pll/pll_main.v
set_global_assignment -name VERILOG_FILE source/pll/pll_reconf_rom.v
set_global_assignment -name VERILOG_FILE source/misc/edge_detect.v
set_global_assignment -name VERILOG_FILE source/misc/data_cross.v
set_global_assignment -name VERILOG_FILE source/misc/delayline.v
set_global_assignment -name VERILOG_FILE source/misc/Flag_CrossDomain.v
set_global_assignment -name VERILOG_FILE source/misc/bcdcounter.v
set_global_assignment -name VERILOG_FILE source/misc/Binary_to_BCD.v
set_global_assignment -name VERILOG_FILE source/sensor.v
set_global_assignment -name VERILOG_FILE source/configuration.v
set_global_assignment -name VERILOG_FILE source/measure.v
set_global_assignment -name VERILOG_FILE source/video.v
set_global_assignment -name VERILOG_FILE source/video/video_config.v
set_global_assignment -name VERILOG_FILE source/video/timingsgen.v
set_global_assignment -name VERILOG_FILE source/video/textgen.v
set_global_assignment -name VERILOG_FILE source/video/videogen.v
set_global_assignment -name VERILOG_FILE source/typedef.v
set_global_assignment -name VERILOG_FILE source/tfp410/tfp410.v
set_global_assignment -name VERILOG_FILE source/tfp410/I2C.v
set_global_assignment -name VHDL_FILE source/tfp410/i2c_master.vhd
set_global_assignment -name VERILOG_FILE source/char_rom/char_rom.v
set_global_assignment -name VERILOG_FILE source/char_rom/resolution.v
set_global_assignment -name VERILOG_FILE source/char_rom/lagdisplay.v
########################################################
# pin assignments
########################################################
set_location_assignment PIN_27 -to clock
set_location_assignment PIN_33 -to DVI_CLOCK
set_location_assignment PIN_6 -to RES_CONFIG[0]
set_location_assignment PIN_5 -to RES_CONFIG[1]
set_location_assignment PIN_4 -to RES_CONFIG[2]
set_location_assignment PIN_8 -to RES_CONFIG[3]
set_location_assignment PIN_9 -to RES_CONFIG[4]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RES_CONFIG[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RES_CONFIG[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RES_CONFIG[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RES_CONFIG[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RES_CONFIG[4]
set_location_assignment PIN_40 -to TFP410_reset
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TFP410_reset
set_location_assignment PIN_115 -to LED
set_location_assignment PIN_79 -to DVI_RED[7]
set_location_assignment PIN_78 -to DVI_RED[6]
set_location_assignment PIN_76 -to DVI_RED[5]
set_location_assignment PIN_75 -to DVI_RED[4]
set_location_assignment PIN_74 -to DVI_RED[3]
set_location_assignment PIN_70 -to DVI_RED[2]
set_location_assignment PIN_69 -to DVI_RED[1]
set_location_assignment PIN_68 -to DVI_RED[0]
set_location_assignment PIN_67 -to DVI_GREEN[7]
set_location_assignment PIN_65 -to DVI_GREEN[6]
set_location_assignment PIN_63 -to DVI_GREEN[5]
set_location_assignment PIN_62 -to DVI_GREEN[4]
set_location_assignment PIN_61 -to DVI_GREEN[3]
set_location_assignment PIN_60 -to DVI_GREEN[2]
set_location_assignment PIN_59 -to DVI_GREEN[1]
set_location_assignment PIN_54 -to DVI_GREEN[0]
set_location_assignment PIN_53 -to DVI_BLUE[7]
set_location_assignment PIN_52 -to DVI_BLUE[6]
set_location_assignment PIN_51 -to DVI_BLUE[5]
set_location_assignment PIN_50 -to DVI_BLUE[4]
set_location_assignment PIN_49 -to DVI_BLUE[3]
set_location_assignment PIN_48 -to DVI_BLUE[2]
set_location_assignment PIN_47 -to DVI_BLUE[1]
set_location_assignment PIN_46 -to DVI_BLUE[0]
set_location_assignment PIN_44 -to DVI_DE
set_location_assignment PIN_42 -to DVI_HSYNC
set_location_assignment PIN_41 -to DVI_VSYNC
set_location_assignment PIN_39 -to SDA
# Error (18496): The Output SCL in pin location 28 (pad_956) is too close to PLL clock input pin (clock) in pin location 27 (pad_0) File: /build/source/lagtester.v Line: 2
#set_location_assignment PIN_28 -to SCL
set_location_assignment PIN_24 -to SCL
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDA
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SCL
set_location_assignment PIN_7 -to SENSOR
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to SENSOR
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clock
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_CLOCK
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to RES_CONFIG[0]
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to RES_CONFIG[1]
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to RES_CONFIG[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_RED[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_RED[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_RED[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_RED[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_RED[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_RED[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_RED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_RED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_GREEN[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_GREEN[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_GREEN[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_GREEN[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_GREEN[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_GREEN[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_GREEN[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_GREEN[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_BLUE[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_BLUE[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_BLUE[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_BLUE[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_BLUE[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_BLUE[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_BLUE[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_BLUE[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_DE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_HSYNC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_VSYNC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SCL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TFP410_reset
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED