forked from zylin/Verilog_VCD
-
Notifications
You must be signed in to change notification settings - Fork 22
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
vcdcat misses an input signal #36
Comments
Hi, can you provide a sample vcd to reproduce? |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
I have in my .vcd file, a variable called
tb.clk
. We can see it here like this ->But when I do
vcdcat test/rotate100/wave.vcd
, I get a .txt file that is like this:Why does it skip the
tb.clk
signal all together?The text was updated successfully, but these errors were encountered: