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At the moment, I haven't looked at the read/write ASM so I want to remember to look to see if the xor's use a memory op to ensure 2-load 2-store on 4IPC chips.
- Casey
The text was updated successfully, but these errors were encountered:
At the moment, I haven't looked at the read/write ASM so I want to remember to look to see if the xor's use a memory op to ensure 2-load 2-store on 4IPC chips.
- Casey
The text was updated successfully, but these errors were encountered: