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Yosys now has a Python API using boost_python. Enable it with: sudo make install ENABLE_PYOSYS=1 ENABLE_LIBYOSYS=1
We can use this to encode the Verilog directly from RTLIL instead of going through the BTOR format. This would give us much better control over the design and even allow us to dynamically run passes based on the contents of the design.
The text was updated successfully, but these errors were encountered:
Hello, unfortunately this feature doesn't exist in Pono either. However, it would be a nice feature. It would probably make more sense to do this through C++ in Pono (but of course it could be accessed through the Python bindings also). I can add it as an enhancement idea there as well.
Yosys now has a Python API using
boost_python
. Enable it with:sudo make install ENABLE_PYOSYS=1 ENABLE_LIBYOSYS=1
We can use this to encode the Verilog directly from RTLIL instead of going through the BTOR format. This would give us much better control over the design and even allow us to dynamically run passes based on the contents of the design.
The text was updated successfully, but these errors were encountered: