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lines changed Original file line number Diff line number Diff line change @@ -15,6 +15,8 @@ class IO:
1515
1616 sim.io.en_enq
1717 sim.io.en_enq = 1
18+
19+ Note: We assume that there is no wires named sim_object
1820 """
1921 def __init__ (self , pyverilator_sim ):
2022 self .sim_object = pyverilator_sim
@@ -43,6 +45,7 @@ class Internals:
4345 """ Exposes the internal signals of the verilator model with standard python syntax:
4446
4547 sim.internals.__T243
48+ Note: We assume that there is no wires named sim_object
4649 """
4750 def __init__ (self , pyverilator_sim ):
4851 self .sim_object = pyverilator_sim
@@ -447,11 +450,6 @@ def send_signals_to_gtkwave(self, signal_names):
447450 if num_found_signals < len (signal_names ):
448451 raise ValueError ('send_signals_to_gtkwave was only able to send %d of %d signals' % (num_found_signals , len (signal_names )))
449452
450- def send_reg_to_gtkwave (self , reg_name ):
451- if not self .gtkwave_active :
452- raise ValueError ('send_reg_to_gtkwave() requires GTKWave to be started using start_gtkwave()' )
453- self .send_signals_to_gtkwave (reg_name )
454-
455453 def send_signal_to_gtkwave (self , signal_name ):
456454 if not self .gtkwave_active :
457455 raise ValueError ('send_signal_to_gtkwave() requires GTKWave to be started using start_gtkwave()' )
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