Add ability to build multiple verilog files and set top module

[quetric]

Currently it doesnt seem like PyVerilator supports providing explicit lists of Verilog files to pass down to Verilator, or setting the top module explicitly. Verilator will only find the files automatically if they are of the same name as the modules being searched for, which is not always the case. Is there any plan to support these features in PyVerilator?

I've attached an example Verilog codebase generated by Xilinx Vivado HLS 2019.2 where some utility modules are placed in regslice_core.v. The correct way to verilate this project is:

/usr/bin/verilator_bin -Wno-fatal -Mdir . --CFLAGS '-fPIC --std=c++11' --trace --trace-depth 2 --cc Thresholding_Batch_0_Thresholding_Batch_0.v regslice_core.v --top-module Thresholding_Batch_0_Thresholding_Batch_0 --exe pyverilator_wrapper.cpp

However, building from PyVerilator fails:

[example.zip](https://github.com/csail-csg/pyverilator/files/4598719/example.zip)
In [2]: pyverilator.PyVerilator.build('Thresholding_Batch_0_Thresholding_Batch_0.v')                                                                  
%Error: Thresholding_Batch_0_Thresholding_Batch_0.v:86: Cannot find file containing module: regslice_both
%Error: Thresholding_Batch_0_Thresholding_Batch_0.v:86: This may be because there's no search path specified with -I<dir>.
%Error: Thresholding_Batch_0_Thresholding_Batch_0.v:86: Looked in:
%Error: Thresholding_Batch_0_Thresholding_Batch_0.v:86:       regslice_both
%Error: Thresholding_Batch_0_Thresholding_Batch_0.v:86:       regslice_both.v
%Error: Thresholding_Batch_0_Thresholding_Batch_0.v:86:       regslice_both.sv
%Error: Thresholding_Batch_0_Thresholding_Batch_0.v:86:       /tmp/Thresholding_Batch_0_Thresholding_Batch_0-jfo1mavd/regslice_both
%Error: Thresholding_Batch_0_Thresholding_Batch_0.v:86:       /tmp/Thresholding_Batch_0_Thresholding_Batch_0-jfo1mavd/regslice_both.v
%Error: Thresholding_Batch_0_Thresholding_Batch_0.v:86:       /tmp/Thresholding_Batch_0_Thresholding_Batch_0-jfo1mavd/regslice_both.sv
%Error: Thresholding_Batch_0_Thresholding_Batch_0.v:100: Cannot find file containing module: regslice_both
%Warning-WIDTH: Thresholding_Batch_0_Thresholding_Batch_0.v:171: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.
%Error: Exiting due to 10 error(s)
%Error: See the manual and http://www.veripool.org/verilator for more assistance.
%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal -Mdir /tmp/Thresholding_Batch_0_Thresholding_Batch_0-jfo1mavd --CFLAGS '-fPIC --std=c++11' --trace --trace-depth 2 --cc Thresholding_Batch_0_Thresholding_Batch_0.v --exe /tmp/Thresholding_Batch_0_Thresholding_Batch_0-jfo1mavd/pyverilator_wrapper.cpp
---------------------------------------------------------------------------
FileNotFoundError                         Traceback (most recent call last)
<ipython-input-2-30fd53adebef> in <module>
----> 1 pyverilator.PyVerilator.build('Thresholding_Batch_0_Thresholding_Batch_0.v')

/workspace/pyverilator/pyverilator/pyverilator.py in build(cls, top_verilog_file, verilog_path, build_dir, json_data, gen_only, trace_depth)
    455                 return None
    456 
--> 457         with open(verilator_h_file) as f:
    458             for line in f:
    459                 result = search_for_signal_decl('IN', line)

FileNotFoundError: [Errno 2] No such file or directory: '/tmp/Thresholding_Batch_0_Thresholding_Batch_0-jfo1mavd/VThresholding_Batch_0_Thresholding_Batch_0.h'

[quetric]

example.zip