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samsoniuksamsoniuk
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Merge pull request #83 from oharboe/boards-openroad
Boards openroad added
2 parents 5527b35 + 8e62d40 commit 5e1da2e

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‎.bazelversion

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7.4.0

‎.gitignore

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iseconfig
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*.a
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*.bin
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bazel-bin
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bazel-darkriscv
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bazel-out
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bazel-testlogs

‎BUILD.bazel

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"""Top level Bazel module, allows access to files by other modules."""
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exports_files(
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glob([
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"rtl/**/*.v",
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"rtl/**/*.vh",
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]),
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visibility = [":__subpackages__"],
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)
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filegroup(
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name = "verilog",
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srcs = glob(
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["rtl/**/*.v"],
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# FIXME delete this on next upgrade of ORFS
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exclude = ["rtl/darksocv.v"],
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) + [
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":darksocv_cleaned",
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],
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visibility = [":__subpackages__"],
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)
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# FIXME delete this on next upgrade of ORFS, it handles $display() statements
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genrule(
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name = "darksocv_cleaned",
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srcs = [
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":rtl/darksocv.v",
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":rtl/config.vh",
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],
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outs = [
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":cleaned/rtl/darksocv_cleaned.v",
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":cleaned/rtl/config.vh",
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],
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cmd = """
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sed -e "/\\$$display/d" $(location :rtl/darksocv.v) > $(location :cleaned/rtl/darksocv_cleaned.v)
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cp $(location :rtl/config.vh) $(location :cleaned/rtl/config.vh)
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""",
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)
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filegroup(
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name = "verilog_include",
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srcs = glob(["rtl/**/*.vh"]),
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visibility = [":__subpackages__"],
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)
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filegroup(
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name = "verilog_data",
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srcs = glob(["src/**/*.mem"]),
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visibility = [":__subpackages__"],
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)

‎MODULE.bazel

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"""Bazel depedencies"""
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module(
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name = "darkriscv",
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version = "0.0.1",
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compatibility_level = 1,
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)
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bazel_dep(name = "bazel-orfs")
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git_override(
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module_name = "bazel-orfs",
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commit = "b16da67e50032682dc6f01252217bfb71cf89260",
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remote = "https://github.com/The-OpenROAD-Project/bazel-orfs.git",
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)
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orfs = use_extension("@bazel-orfs//:extension.bzl", "orfs_repositories")
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orfs.default(
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# To update, find latest at https://hub.docker.com/r/openroad/orfs/tags
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image = "docker.io/openroad/orfs:v3.0-2591-g9bca87d7",
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sha256 = "673181c3b49235cf5b43e386e4cf478d676b797c8b7736a3ed79fc90f4c8acb7",
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)
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use_repo(orfs, "com_github_nixos_patchelf_download")
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use_repo(orfs, "docker_orfs")

‎MODULE.bazel.lock

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‎boards/openroad/BUILD.bazel

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load("@bazel-orfs//:openroad.bzl", "orfs_flow")
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FASTER = {
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# ignore timing repair for now
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"SETUP_SLACK_MARGIN": "-1000",
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"SKIP_REPORT_METRICS": "1",
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"SKIP_LAST_GASP": "1",
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# skip checks for now, faster
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"PWR_NETS_VOLTAGES": "",
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"GND_NETS_VOLTAGES": "",
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}
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# SRAMs are specific to PDK, mock one here by
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# creating it from flip flops and use mock_area
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# to reduce the size of the SRAM to something that
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# is a bit more reasonable.
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orfs_flow(
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name = "darkram",
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abstract_stage = "cts",
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arguments = FASTER | {
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"CORE_UTILIZATION": "10",
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"SYNTH_MEMORY_MAX_BITS": "65536",
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"MACRO_BLOCKAGE_HALO": "0",
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"PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCK_grid_strategy.tcl",
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},
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# The width/height of a real SRAM might be, say,
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# 25% of that of a flip flop based SRAM.
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mock_area = 0.25,
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sources = {
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"SDC_FILE": [":constraints_darkram.sdc"],
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},
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stage_data = {
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"synth": [
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"//:verilog_data",
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"//:verilog_include",
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],
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},
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# OpenROAD version of the darkram.v file
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verilog_files = [":darkram.v"],
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)
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orfs_flow(
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name = "darksocv",
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arguments = FASTER | {
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"SYNTH_HIERARCHICAL": "1",
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#"SYNTH_MINIMUM_KEEP_SIZE": "1",
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"CORE_UTILIZATION": "40",
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"MIN_ROUTING_LAYER": "M2",
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"MAX_ROUTING_LAYER": "M7",
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"CORE_MARGIN": "2",
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"MACRO_PLACE_HALO": "2 2",
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"PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCKS_grid_strategy.tcl",
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"GDS_ALLOW_EMPTY": "darkram",
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},
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macros = ["darkram_generate_abstract"],
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sources = {
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"SDC_FILE": [":constraints.sdc"],
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},
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stage_data = {
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"synth": [
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"//:verilog_data",
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"//:verilog_include",
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],
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},
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verilog_files = [
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"//:verilog",
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],
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)

‎boards/openroad/README.md

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OpenROAD ASAP7 PDK configuration
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================================
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TL;DR Install Bazelisk and run command below to build and view darksocv in the GUI, Bazelisk handles all depedencies.
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Demonstrates how to set up an [bazel-orfs](https://github.com/The-OpenROAD-Project/bazel-orfs) to build darksocv with [OpenROAD-flow-scripts](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts)
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To build and view [Install Bazelisk](https://bazel.build/install/bazelisk) and run:
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bazelisk run //boards/openroad:darksocv_cts /tmp/cts gui_cts
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Register to register histogram
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------------------------------
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![alt text](reg2reg-histogram.png)
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Estimated routing congestion
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----------------------------
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![alt text](routing-congestion.png)
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Ideas for future work
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=====================
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- reduce clock period
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- darkram.v should consist of serveral SRAMs connected together to be
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a more accurate representation
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- create a mock SRAM representation with somewhat realistic timing
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- add IO constraints to place pins on one edge of the SRAMs and top level
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- reduce area
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[MegaBoom](https://github.com/The-OpenROAD-Project/megaboom) demonstrates a number of techniques to study a design and set up mock SRAMs.

‎boards/openroad/constraints.sdc

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set clk_name XCLK
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set clk_port_name XCLK
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set clk_period 2000
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source $::env(PLATFORM_DIR)/constraints.sdc

‎boards/openroad/constraints_darkram.sdc

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set sdc_version 2.0
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set clk_name CLK
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set clk_port_name CLK
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set clk_period 2000
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set clk_port [get_ports $clk_port_name]
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create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port
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set non_clk_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
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set all_register_outputs [get_pins -of_objects [all_registers] -filter {direction == output}]
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set_max_delay [expr {[info exists in2reg_max] ? $in2reg_max : 80}] -from $non_clk_inputs -to [all_registers]
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set_max_delay [expr {[info exists reg2out_max] ? $reg2out_max : 80}] -from $all_register_outputs -to [all_outputs]
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set_max_delay [expr {[info exists in2out_max] ? $in2out_max : 80}] -from $non_clk_inputs -to [all_outputs]
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# group_path -name in2reg -from $non_clk_inputs -to [all_registers]
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# group_path -name reg2out -from [all_registers] -to [all_outputs]
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# group_path -name in2out -from $non_clk_inputs -to [all_outputs]

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