VHDL Conversion Notes

[darsor]

Main differences in logic between SV and VHDL:

• Signals must be declared at the beginning of the entity, not throughout like in SV
  • Added signal_declaration method to Cpuif classes, removed declarations from templates
• VHDL processes have async and sync resets in different places (SV can have them in the same place)
  • Always generate both async and sync blocks, but one of them uses "if false" as the condition
• Interfaces are only supported in VHDL 2019, which does not yet have widespread tool support
  • Use separate records for input and output
• Arrays must be explicitly defined as new types
  • Arrays are defined as needed for typedef structs
  • Predefined matrices of dimensions 1-5 for std_logic and std_logic_vector with the "_array" suffix, in reg_utils package
• VHDL records can't be anonymous like SV structs
  • Use FlatStructGenerator instead of StructGenerator
• VHDL records don't have a "packed" equivalent
  • These are used for external registers. Use std_logic_vectors instead.
• VHDL enums can't be given integer values directly (used for RDL enumerations in the hwif pkg file)
  • Declared constants in package file
• Operator precedence
  • For example, in SV, & has higher precedence than |. In VHDL, 'and' and 'or' have the same precedence, and parenthesis are required.
• Single-bit values and multi-bit values are different types
  • Literals: for example, '1' vs (others => '1'). VhdlInt AGGREGATE type handles this.
  • Reduction operators only work on multi-bit values. Apply them selectively.
• Numeric types
  • VHDL is has stricter typing, especially with numeric operations (arithmetic, comparisons).
  • By default, declare everything as std_logic_vector and do conversions as necessary
  • In some cases it makes sense to declare as unsigned (e.g., in a self-contained template)
  • Custom overloaded conversion function declared in reg_utils package to make it easier
• Arithmetic operands are not automatically sign-extended in VHDL like in SV
  • Manually sign extend arithmetic operands
• Generate statements require labels
• VHDL identifiers can not contain double underscores ("__"), or start or end with an underscore. The upstream repo used double underscores extensively to replace periods "." in hierarchical namespaces.
  • Use "extended identifiers" with periods (".") for type names. Extended identifiers are wrapped in backslashes ("\")
  • These actual look more readable than the double underscores.
  • This only affects the type definition. Accessing the records is the same.
• In simulation, VHDL expression 'x' /= '0' evaluates to true, while in SV the equivalent evaluates to false.
  • expression occurs in interrupt conditional logic
  • problem appears in interrupt tests, in the first clock cycle
  • changed to or_reduce('x') so that unresolvable bits force the conditional to false