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log-D202403004 #43

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huangxc6 opened this issue Mar 11, 2024 · 9 comments
Open

log-D202403004 #43

huangxc6 opened this issue Mar 11, 2024 · 9 comments

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@huangxc6
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https://github.com/huangxc6/MIT_6.175_6.375_Lab

@huangxc6
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huangxc6 commented Mar 12, 2024

Data: 240310
Learning cost: 4 hours
Completed: Watch the Getting Started video, install the bsv compiler, and learn the bsv examples!

To do:

  • 6.004 video
  • 6.175 lab1

@huangxc6
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huangxc6 commented Mar 12, 2024

Data: 240312
Learning cost: 3 hours
Completed: Lab1

To do:

  • 6.004 video
  • 6.175 Lab2

@huangxc6
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huangxc6 commented Mar 16, 2024

Data: 240316
Learning cost: 7 hours
Completed: 6.175 Lab2
learn bsv grammar, 6.004 combination and sequence logic ppt

To do:

  • 6.004 video
  • 6.175 Lab3

@huangxc6
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huangxc6 commented Mar 23, 2024

Data: 240323
Learning cost: 6 hours
Completed: 6.175 Lab4
learn CM, 6.004 ppt

To do:

  • 6.004 video
  • 6.175 Lab4

@huangxc6
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huangxc6 commented Apr 3, 2024

Data: 240403
Learning cost: 8 hours
Completed: 6.175 Lab4
learn CM,EHR, FIFO. 6.004 ppt
install docker in ubuntu, learn how to use it

To do:

  • 6.175 Lab5

@huangxc6
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huangxc6 commented Apr 29, 2024

Data: 240429
Learning cost: 30 hours
Completed: 6.175 Lab5
learn how to use docker & riscv toolchain.
learn the onecycle and multicycle cpu arch & two stage without/with BTB.
the biggest problem I encountered is that the environment is difficult to configure.
Another problem is that I have little consistent time to advance the project in the past month.

To do:

  • 6.175 Lab6

@huangxc6
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huangxc6 commented May 12, 2024

Data: 240512
Learning cost: 20 hours
Completed: 6.175 Lab6
Learn the sixstage pipeline processor.
Learn the branch target buffer(BTB), branch history table(BHT) and return address stack (RAS).
Learn the chapter 7 BSV Rule Semantics, chapter 8 Concurrent Components, chapter 9 Data Hazards,chapter 10 Branch Prediction.

To do:

  • 6.175 Lab7

@huangxc6
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huangxc6 commented May 14, 2024

Data: 240514
Learning cost: 10 hours
Completed: 6.175 Lab7
Learn how to use the DRAM.
Learn the cache theory and strategy.
Solve the vmh file problem.
Learn and implement six stage pipeline processor with cache.

To do:

  • 6.175 Lab8

@huangxc6
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Data: 240515
Learning cost: 4 hours
Completed: 6.175 Lab8
Learn and implement onecycle processor with exception.

To do:

  • Review and summary the 6.175Lab.

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