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misalehwilldeacon
misaleh
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willdeacon
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iommu/arm-smmu-v3-test: Test masters with stall enabled
At the moment, the SMMUv3 unit tests assume ATS is always enabled, although this is sufficient to test hitless/non-hitless transitions, but exercising other features is useful to check ste/cd population logic (for example the .get_used logic). Add an enum where bits define features per-master, at the moment there is only ATS and STALLs which are mutually exclusive, but this would make it easier to extend with other features in the future. Also, Add 2 more tests for s1 <-> s2 transitions with stalls enabled. Signed-off-by: Mostafa Saleh <smostafa@google.com> Link: https://lore.kernel.org/r/20240830110349.797399-3-smostafa@google.com Signed-off-by: Will Deacon <will@kernel.org>
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‎drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c‎

Lines changed: 62 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,11 @@ static struct mm_struct sva_mm = {
3030
.pgd = (void *)0xdaedbeefdeadbeefULL,
3131
};
3232

33+
enum arm_smmu_test_master_feat {
34+
ARM_SMMU_MASTER_TEST_ATS = BIT(0),
35+
ARM_SMMU_MASTER_TEST_STALL = BIT(1),
36+
};
37+
3338
static bool arm_smmu_entry_differs_in_used_bits(const __le64 *entry,
3439
const __le64 *used_bits,
3540
const __le64 *target,
@@ -164,16 +169,22 @@ static const dma_addr_t fake_cdtab_dma_addr = 0xF0F0F0F0F0F0;
164169

165170
static void arm_smmu_test_make_cdtable_ste(struct arm_smmu_ste *ste,
166171
unsigned int s1dss,
167-
const dma_addr_t dma_addr)
172+
const dma_addr_t dma_addr,
173+
enum arm_smmu_test_master_feat feat)
168174
{
175+
bool ats_enabled = feat & ARM_SMMU_MASTER_TEST_ATS;
176+
bool stall_enabled = feat & ARM_SMMU_MASTER_TEST_STALL;
177+
169178
struct arm_smmu_master master = {
179+
.ats_enabled = ats_enabled,
170180
.cd_table.cdtab_dma = dma_addr,
171181
.cd_table.s1cdmax = 0xFF,
172182
.cd_table.s1fmt = STRTAB_STE_0_S1FMT_64K_L2,
173183
.smmu = &smmu,
184+
.stall_enabled = stall_enabled,
174185
};
175186

176-
arm_smmu_make_cdtable_ste(ste, &master, true, s1dss);
187+
arm_smmu_make_cdtable_ste(ste, &master, ats_enabled, s1dss);
177188
}
178189

179190
static void arm_smmu_v3_write_ste_test_bypass_to_abort(struct kunit *test)
@@ -204,7 +215,7 @@ static void arm_smmu_v3_write_ste_test_cdtable_to_abort(struct kunit *test)
204215
struct arm_smmu_ste ste;
205216

206217
arm_smmu_test_make_cdtable_ste(&ste, STRTAB_STE_1_S1DSS_SSID0,
207-
fake_cdtab_dma_addr);
218+
fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS);
208219
arm_smmu_v3_test_ste_expect_hitless_transition(test, &ste, &abort_ste,
209220
NUM_EXPECTED_SYNCS(2));
210221
}
@@ -214,7 +225,7 @@ static void arm_smmu_v3_write_ste_test_abort_to_cdtable(struct kunit *test)
214225
struct arm_smmu_ste ste;
215226

216227
arm_smmu_test_make_cdtable_ste(&ste, STRTAB_STE_1_S1DSS_SSID0,
217-
fake_cdtab_dma_addr);
228+
fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS);
218229
arm_smmu_v3_test_ste_expect_hitless_transition(test, &abort_ste, &ste,
219230
NUM_EXPECTED_SYNCS(2));
220231
}
@@ -224,7 +235,7 @@ static void arm_smmu_v3_write_ste_test_cdtable_to_bypass(struct kunit *test)
224235
struct arm_smmu_ste ste;
225236

226237
arm_smmu_test_make_cdtable_ste(&ste, STRTAB_STE_1_S1DSS_SSID0,
227-
fake_cdtab_dma_addr);
238+
fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS);
228239
arm_smmu_v3_test_ste_expect_hitless_transition(test, &ste, &bypass_ste,
229240
NUM_EXPECTED_SYNCS(3));
230241
}
@@ -234,7 +245,7 @@ static void arm_smmu_v3_write_ste_test_bypass_to_cdtable(struct kunit *test)
234245
struct arm_smmu_ste ste;
235246

236247
arm_smmu_test_make_cdtable_ste(&ste, STRTAB_STE_1_S1DSS_SSID0,
237-
fake_cdtab_dma_addr);
248+
fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS);
238249
arm_smmu_v3_test_ste_expect_hitless_transition(test, &bypass_ste, &ste,
239250
NUM_EXPECTED_SYNCS(3));
240251
}
@@ -245,9 +256,9 @@ static void arm_smmu_v3_write_ste_test_cdtable_s1dss_change(struct kunit *test)
245256
struct arm_smmu_ste s1dss_bypass;
246257

247258
arm_smmu_test_make_cdtable_ste(&ste, STRTAB_STE_1_S1DSS_SSID0,
248-
fake_cdtab_dma_addr);
259+
fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS);
249260
arm_smmu_test_make_cdtable_ste(&s1dss_bypass, STRTAB_STE_1_S1DSS_BYPASS,
250-
fake_cdtab_dma_addr);
261+
fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS);
251262

252263
/*
253264
* Flipping s1dss on a CD table STE only involves changes to the second
@@ -265,7 +276,7 @@ arm_smmu_v3_write_ste_test_s1dssbypass_to_stebypass(struct kunit *test)
265276
struct arm_smmu_ste s1dss_bypass;
266277

267278
arm_smmu_test_make_cdtable_ste(&s1dss_bypass, STRTAB_STE_1_S1DSS_BYPASS,
268-
fake_cdtab_dma_addr);
279+
fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS);
269280
arm_smmu_v3_test_ste_expect_hitless_transition(
270281
test, &s1dss_bypass, &bypass_ste, NUM_EXPECTED_SYNCS(2));
271282
}
@@ -276,16 +287,20 @@ arm_smmu_v3_write_ste_test_stebypass_to_s1dssbypass(struct kunit *test)
276287
struct arm_smmu_ste s1dss_bypass;
277288

278289
arm_smmu_test_make_cdtable_ste(&s1dss_bypass, STRTAB_STE_1_S1DSS_BYPASS,
279-
fake_cdtab_dma_addr);
290+
fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS);
280291
arm_smmu_v3_test_ste_expect_hitless_transition(
281292
test, &bypass_ste, &s1dss_bypass, NUM_EXPECTED_SYNCS(2));
282293
}
283294

284295
static void arm_smmu_test_make_s2_ste(struct arm_smmu_ste *ste,
285-
bool ats_enabled)
296+
enum arm_smmu_test_master_feat feat)
286297
{
298+
bool ats_enabled = feat & ARM_SMMU_MASTER_TEST_ATS;
299+
bool stall_enabled = feat & ARM_SMMU_MASTER_TEST_STALL;
287300
struct arm_smmu_master master = {
301+
.ats_enabled = ats_enabled,
288302
.smmu = &smmu,
303+
.stall_enabled = stall_enabled,
289304
};
290305
struct io_pgtable io_pgtable = {};
291306
struct arm_smmu_domain smmu_domain = {
@@ -308,7 +323,7 @@ static void arm_smmu_v3_write_ste_test_s2_to_abort(struct kunit *test)
308323
{
309324
struct arm_smmu_ste ste;
310325

311-
arm_smmu_test_make_s2_ste(&ste, true);
326+
arm_smmu_test_make_s2_ste(&ste, ARM_SMMU_MASTER_TEST_ATS);
312327
arm_smmu_v3_test_ste_expect_hitless_transition(test, &ste, &abort_ste,
313328
NUM_EXPECTED_SYNCS(2));
314329
}
@@ -317,7 +332,7 @@ static void arm_smmu_v3_write_ste_test_abort_to_s2(struct kunit *test)
317332
{
318333
struct arm_smmu_ste ste;
319334

320-
arm_smmu_test_make_s2_ste(&ste, true);
335+
arm_smmu_test_make_s2_ste(&ste, ARM_SMMU_MASTER_TEST_ATS);
321336
arm_smmu_v3_test_ste_expect_hitless_transition(test, &abort_ste, &ste,
322337
NUM_EXPECTED_SYNCS(2));
323338
}
@@ -326,7 +341,7 @@ static void arm_smmu_v3_write_ste_test_s2_to_bypass(struct kunit *test)
326341
{
327342
struct arm_smmu_ste ste;
328343

329-
arm_smmu_test_make_s2_ste(&ste, true);
344+
arm_smmu_test_make_s2_ste(&ste, ARM_SMMU_MASTER_TEST_ATS);
330345
arm_smmu_v3_test_ste_expect_hitless_transition(test, &ste, &bypass_ste,
331346
NUM_EXPECTED_SYNCS(2));
332347
}
@@ -335,7 +350,7 @@ static void arm_smmu_v3_write_ste_test_bypass_to_s2(struct kunit *test)
335350
{
336351
struct arm_smmu_ste ste;
337352

338-
arm_smmu_test_make_s2_ste(&ste, true);
353+
arm_smmu_test_make_s2_ste(&ste, ARM_SMMU_MASTER_TEST_ATS);
339354
arm_smmu_v3_test_ste_expect_hitless_transition(test, &bypass_ste, &ste,
340355
NUM_EXPECTED_SYNCS(2));
341356
}
@@ -346,8 +361,8 @@ static void arm_smmu_v3_write_ste_test_s1_to_s2(struct kunit *test)
346361
struct arm_smmu_ste s2_ste;
347362

348363
arm_smmu_test_make_cdtable_ste(&s1_ste, STRTAB_STE_1_S1DSS_SSID0,
349-
fake_cdtab_dma_addr);
350-
arm_smmu_test_make_s2_ste(&s2_ste, true);
364+
fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS);
365+
arm_smmu_test_make_s2_ste(&s2_ste, ARM_SMMU_MASTER_TEST_ATS);
351366
arm_smmu_v3_test_ste_expect_hitless_transition(test, &s1_ste, &s2_ste,
352367
NUM_EXPECTED_SYNCS(3));
353368
}
@@ -358,8 +373,8 @@ static void arm_smmu_v3_write_ste_test_s2_to_s1(struct kunit *test)
358373
struct arm_smmu_ste s2_ste;
359374

360375
arm_smmu_test_make_cdtable_ste(&s1_ste, STRTAB_STE_1_S1DSS_SSID0,
361-
fake_cdtab_dma_addr);
362-
arm_smmu_test_make_s2_ste(&s2_ste, true);
376+
fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS);
377+
arm_smmu_test_make_s2_ste(&s2_ste, ARM_SMMU_MASTER_TEST_ATS);
363378
arm_smmu_v3_test_ste_expect_hitless_transition(test, &s2_ste, &s1_ste,
364379
NUM_EXPECTED_SYNCS(3));
365380
}
@@ -375,9 +390,9 @@ static void arm_smmu_v3_write_ste_test_non_hitless(struct kunit *test)
375390
* s1 dss field in the same update.
376391
*/
377392
arm_smmu_test_make_cdtable_ste(&ste, STRTAB_STE_1_S1DSS_SSID0,
378-
fake_cdtab_dma_addr);
393+
fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS);
379394
arm_smmu_test_make_cdtable_ste(&ste_2, STRTAB_STE_1_S1DSS_BYPASS,
380-
0x4B4B4b4B4B);
395+
0x4B4B4b4B4B, ARM_SMMU_MASTER_TEST_ATS);
381396
arm_smmu_v3_test_ste_expect_non_hitless_transition(
382397
test, &ste, &ste_2, NUM_EXPECTED_SYNCS(3));
383398
}
@@ -503,6 +518,30 @@ static void arm_smmu_test_make_sva_release_cd(struct arm_smmu_cd *cd,
503518
arm_smmu_make_sva_cd(cd, &master, NULL, asid);
504519
}
505520

521+
static void arm_smmu_v3_write_ste_test_s1_to_s2_stall(struct kunit *test)
522+
{
523+
struct arm_smmu_ste s1_ste;
524+
struct arm_smmu_ste s2_ste;
525+
526+
arm_smmu_test_make_cdtable_ste(&s1_ste, STRTAB_STE_1_S1DSS_SSID0,
527+
fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_STALL);
528+
arm_smmu_test_make_s2_ste(&s2_ste, ARM_SMMU_MASTER_TEST_STALL);
529+
arm_smmu_v3_test_ste_expect_hitless_transition(test, &s1_ste, &s2_ste,
530+
NUM_EXPECTED_SYNCS(3));
531+
}
532+
533+
static void arm_smmu_v3_write_ste_test_s2_to_s1_stall(struct kunit *test)
534+
{
535+
struct arm_smmu_ste s1_ste;
536+
struct arm_smmu_ste s2_ste;
537+
538+
arm_smmu_test_make_cdtable_ste(&s1_ste, STRTAB_STE_1_S1DSS_SSID0,
539+
fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_STALL);
540+
arm_smmu_test_make_s2_ste(&s2_ste, ARM_SMMU_MASTER_TEST_STALL);
541+
arm_smmu_v3_test_ste_expect_hitless_transition(test, &s2_ste, &s1_ste,
542+
NUM_EXPECTED_SYNCS(3));
543+
}
544+
506545
static void arm_smmu_v3_write_cd_test_sva_clear(struct kunit *test)
507546
{
508547
struct arm_smmu_cd cd = {};
@@ -547,6 +586,8 @@ static struct kunit_case arm_smmu_v3_test_cases[] = {
547586
KUNIT_CASE(arm_smmu_v3_write_ste_test_non_hitless),
548587
KUNIT_CASE(arm_smmu_v3_write_cd_test_s1_clear),
549588
KUNIT_CASE(arm_smmu_v3_write_cd_test_s1_change_asid),
589+
KUNIT_CASE(arm_smmu_v3_write_ste_test_s1_to_s2_stall),
590+
KUNIT_CASE(arm_smmu_v3_write_ste_test_s2_to_s1_stall),
550591
KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_clear),
551592
KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_release),
552593
{},

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