1111 * ---------------------------------------------------------------------- 
1212 * |             Level            |   Last Value Used  |     Holes	| 
1313 * ---------------------------------------------------------------------- 
14-  * | Module Init and Probe        |       0x015b       | 0x4b,0xba,0xfa | 
15-  * |                              |                    | 0x0x015a	| 
16-  * | Mailbox commands             |       0x1187       | 0x111a-0x111b  | 
17-  * |                              |                    | 0x1155-0x1158  | 
18-  * |                              |                    | 0x1018-0x1019  | 
14+  * | Module Init and Probe        |       0x017d       | 0x004b,0x0141	| 
15+  * |                              |                    | 0x0144,0x0146	| 
16+  * |                              |                    | 0x015b-0x0160	| 
17+  * |                              |                    | 0x016e-0x0170	| 
18+  * | Mailbox commands             |       0x1187       | 0x1018-0x1019	| 
19+  * |                              |                    | 0x10ca         | 
1920 * |                              |                    | 0x1115-0x1116  | 
20-  * |                              |                    | 0x10ca		| 
21+  * |                              |                    | 0x111a-0x111b	| 
22+  * |                              |                    | 0x1155-0x1158  | 
2123 * | Device Discovery             |       0x2095       | 0x2020-0x2022, | 
2224 * |                              |                    | 0x2011-0x2012, | 
2325 * |                              |                    | 0x2016         | 
3335 * |                              |                    | 0x5084,0x5075	| 
3436 * |                              |                    | 0x503d,0x5044  | 
3537 * | Timer Routines               |       0x6012       |                | 
36-  * | User Space Interactions      |       0x70e1       | 0x7018,0x702e, | 
37-  * |                              |                    | 0x7020,0x7024, | 
38-  * |                              |                    | 0x7039,0x7045, | 
39-  * |                              |                    | 0x7073-0x7075, | 
40-  * |                              |                    | 0x707b,0x708c, | 
41-  * |                              |                    | 0x70a5,0x70a6, | 
42-  * |                              |                    | 0x70a8,0x70ab, | 
43-  * |                              |                    | 0x70ad-0x70ae, | 
44-  * |                              |                    | 0x70d1-0x70db, | 
45-  * |                              |                    | 0x7047,0x703b	| 
46-  * |                              |                    | 0x70de-0x70df, | 
38+  * | User Space Interactions      |       0x70e2       | 0x7018,0x702e  | 
39+  * |				  |		       | 0x7020,0x7024  | 
40+  * |                              |                    | 0x7039,0x7045  | 
41+  * |                              |                    | 0x7073-0x7075  | 
42+  * |                              |                    | 0x70a5-0x70a6  | 
43+  * |                              |                    | 0x70a8,0x70ab  | 
44+  * |                              |                    | 0x70ad-0x70ae  | 
45+  * |                              |                    | 0x70d7-0x70db  | 
46+  * |                              |                    | 0x70de-0x70df  | 
4747 * | Task Management              |       0x803d       | 0x8025-0x8026  | 
4848 * |                              |                    | 0x800b,0x8039  | 
4949 * | AER/EEH                      |       0x9011       |		| 
5959 * |                              |                    | 0xb13c-0xb140  | 
6060 * |                              |                    | 0xb149		| 
6161 * | MultiQ                       |       0xc00c       |		| 
62-  * | Misc                         |       0xd010       |		| 
62+  * | Misc                         |       0xd2ff       | 0xd017-0xd019	| 
63+  * |                              |                    | 0xd020		| 
64+  * |                              |                    | 0xd02e-0xd0ff	| 
65+  * |                              |                    | 0xd101-0xd1fe	| 
66+  * |                              |                    | 0xd212-0xd2fe	| 
6367 * | Target Mode		  |	  0xe070       | 0xe021		| 
6468 * | Target Mode Management	  |	  0xf072       | 0xf002-0xf003	| 
6569 * |                              |                    | 0xf046-0xf049  | 
@@ -104,7 +108,87 @@ qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
104108	return  ptr  +  (rsp -> length  *  sizeof (response_t ));
105109}
106110
107- static  int 
111+ int 
112+ qla27xx_dump_mpi_ram (struct  qla_hw_data  * ha , uint32_t  addr , uint32_t  * ram ,
113+ 	uint32_t  ram_dwords , void  * * nxt )
114+ {
115+ 	int  rval ;
116+ 	uint32_t  cnt , stat , timer , dwords , idx ;
117+ 	uint16_t  mb0 , mb1 ;
118+ 	struct  device_reg_24xx  __iomem  * reg  =  & ha -> iobase -> isp24 ;
119+ 	dma_addr_t  dump_dma  =  ha -> gid_list_dma ;
120+ 	uint32_t  * dump  =  (uint32_t  * )ha -> gid_list ;
121+ 
122+ 	rval  =  QLA_SUCCESS ;
123+ 	mb0  =  0 ;
124+ 
125+ 	WRT_REG_WORD (& reg -> mailbox0 , MBC_LOAD_DUMP_MPI_RAM );
126+ 	clear_bit (MBX_INTERRUPT , & ha -> mbx_cmd_flags );
127+ 
128+ 	dwords  =  qla2x00_gid_list_size (ha ) / 4 ;
129+ 	for  (cnt  =  0 ; cnt  <  ram_dwords  &&  rval  ==  QLA_SUCCESS ;
130+ 	    cnt  +=  dwords , addr  +=  dwords ) {
131+ 		if  (cnt  +  dwords  >  ram_dwords )
132+ 			dwords  =  ram_dwords  -  cnt ;
133+ 
134+ 		WRT_REG_WORD (& reg -> mailbox1 , LSW (addr ));
135+ 		WRT_REG_WORD (& reg -> mailbox8 , MSW (addr ));
136+ 
137+ 		WRT_REG_WORD (& reg -> mailbox2 , MSW (dump_dma ));
138+ 		WRT_REG_WORD (& reg -> mailbox3 , LSW (dump_dma ));
139+ 		WRT_REG_WORD (& reg -> mailbox6 , MSW (MSD (dump_dma )));
140+ 		WRT_REG_WORD (& reg -> mailbox7 , LSW (MSD (dump_dma )));
141+ 
142+ 		WRT_REG_WORD (& reg -> mailbox4 , MSW (dwords ));
143+ 		WRT_REG_WORD (& reg -> mailbox5 , LSW (dwords ));
144+ 
145+ 		WRT_REG_WORD (& reg -> mailbox9 , 0 );
146+ 		WRT_REG_DWORD (& reg -> hccr , HCCRX_SET_HOST_INT );
147+ 
148+ 		ha -> flags .mbox_int  =  0 ;
149+ 		for  (timer  =  6000000 ; timer ; timer -- ) {
150+ 			/* Check for pending interrupts. */ 
151+ 			stat  =  RD_REG_DWORD (& reg -> host_status );
152+ 			if  (stat  &  HSRX_RISC_INT ) {
153+ 				stat  &= 0xff ;
154+ 
155+ 				if  (stat  ==  0x1  ||  stat  ==  0x2  || 
156+ 				    stat  ==  0x10  ||  stat  ==  0x11 ) {
157+ 					set_bit (MBX_INTERRUPT ,
158+ 					    & ha -> mbx_cmd_flags );
159+ 
160+ 					mb0  =  RD_REG_WORD (& reg -> mailbox0 );
161+ 					mb1  =  RD_REG_WORD (& reg -> mailbox1 );
162+ 
163+ 					WRT_REG_DWORD (& reg -> hccr ,
164+ 					    HCCRX_CLR_RISC_INT );
165+ 					RD_REG_DWORD (& reg -> hccr );
166+ 					break ;
167+ 				}
168+ 
169+ 				/* Clear this intr; it wasn't a mailbox intr */ 
170+ 				WRT_REG_DWORD (& reg -> hccr , HCCRX_CLR_RISC_INT );
171+ 				RD_REG_DWORD (& reg -> hccr );
172+ 			}
173+ 			udelay (5 );
174+ 		}
175+ 		ha -> flags .mbox_int  =  1 ;
176+ 
177+ 		if  (test_and_clear_bit (MBX_INTERRUPT , & ha -> mbx_cmd_flags )) {
178+ 			rval  =  mb0  &  MBS_MASK ;
179+ 			for  (idx  =  0 ; idx  <  dwords ; idx ++ )
180+ 				ram [cnt  +  idx ] =  IS_QLA27XX (ha ) ?
181+ 				    le32_to_cpu (dump [idx ]) : swab32 (dump [idx ]);
182+ 		} else  {
183+ 			rval  =  QLA_FUNCTION_FAILED ;
184+ 		}
185+ 	}
186+ 
187+ 	* nxt  =  rval  ==  QLA_SUCCESS  ? & ram [cnt ] : NULL ;
188+ 	return  rval ;
189+ }
190+ 
191+ int 
108192qla24xx_dump_ram (struct  qla_hw_data  * ha , uint32_t  addr , uint32_t  * ram ,
109193    uint32_t  ram_dwords , void  * * nxt )
110194{
@@ -139,6 +223,7 @@ qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
139223		WRT_REG_WORD (& reg -> mailbox5 , LSW (dwords ));
140224		WRT_REG_DWORD (& reg -> hccr , HCCRX_SET_HOST_INT );
141225
226+ 		ha -> flags .mbox_int  =  0 ;
142227		for  (timer  =  6000000 ; timer ; timer -- ) {
143228			/* Check for pending interrupts. */ 
144229			stat  =  RD_REG_DWORD (& reg -> host_status );
@@ -164,11 +249,13 @@ qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
164249			}
165250			udelay (5 );
166251		}
252+ 		ha -> flags .mbox_int  =  1 ;
167253
168254		if  (test_and_clear_bit (MBX_INTERRUPT , & ha -> mbx_cmd_flags )) {
169255			rval  =  mb0  &  MBS_MASK ;
170256			for  (idx  =  0 ; idx  <  dwords ; idx ++ )
171- 				ram [cnt  +  idx ] =  swab32 (dump [idx ]);
257+ 				ram [cnt  +  idx ] =  IS_QLA27XX (ha ) ?
258+ 				    le32_to_cpu (dump [idx ]) : swab32 (dump [idx ]);
172259		} else  {
173260			rval  =  QLA_FUNCTION_FAILED ;
174261		}
@@ -208,7 +295,7 @@ qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
208295	return  buf ;
209296}
210297
211- static   inline   int 
298+ int 
212299qla24xx_pause_risc (struct  device_reg_24xx  __iomem  * reg )
213300{
214301	int  rval  =  QLA_SUCCESS ;
@@ -227,7 +314,7 @@ qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
227314	return  rval ;
228315}
229316
230- static   int 
317+ int 
231318qla24xx_soft_reset (struct  qla_hw_data  * ha )
232319{
233320	int  rval  =  QLA_SUCCESS ;
@@ -537,7 +624,7 @@ qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
537624	struct  qla2xxx_mq_chain  * mq  =  ptr ;
538625	device_reg_t  __iomem  * reg ;
539626
540- 	if  (!ha -> mqenable  ||  IS_QLA83XX (ha ))
627+ 	if  (!ha -> mqenable  ||  IS_QLA83XX (ha )  ||   IS_QLA27XX ( ha ) )
541628		return  ptr ;
542629
543630	mq  =  ptr ;
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