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ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_mem_ret
As per the latest revision F of public TRM for DRA7/AM57xx SoCs SPRUHZ6F[1] (April 2016), with the exception of MPU power domain, all other power domains do not have memories capable of retention since they all operate in either "ON" or "OFF" mode. For these power states, the retention state for memories are basically ignored by PRCM and does not require to be programmed. [1] http://www.ti.com/lit/pdf/spruhz6 Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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‎arch/arm/mach-omap2/powerdomains7xx_data.c‎

Lines changed: 0 additions & 65 deletions
Original file line numberDiff line numberDiff line change
@@ -37,12 +37,6 @@ static struct powerdomain iva_7xx_pwrdm = {
3737
.prcm_partition = DRA7XX_PRM_PARTITION,
3838
.pwrsts = PWRSTS_OFF_ON,
3939
.banks = 4,
40-
.pwrsts_mem_ret = {
41-
[0] = PWRSTS_OFF_RET, /* hwa_mem */
42-
[1] = PWRSTS_OFF_RET, /* sl2_mem */
43-
[2] = PWRSTS_OFF_RET, /* tcm1_mem */
44-
[3] = PWRSTS_OFF_RET, /* tcm2_mem */
45-
},
4640
.pwrsts_mem_on = {
4741
[0] = PWRSTS_ON, /* hwa_mem */
4842
[1] = PWRSTS_ON, /* sl2_mem */
@@ -76,10 +70,6 @@ static struct powerdomain ipu_7xx_pwrdm = {
7670
.prcm_partition = DRA7XX_PRM_PARTITION,
7771
.pwrsts = PWRSTS_OFF_ON,
7872
.banks = 2,
79-
.pwrsts_mem_ret = {
80-
[0] = PWRSTS_OFF_RET, /* aessmem */
81-
[1] = PWRSTS_OFF_RET, /* periphmem */
82-
},
8373
.pwrsts_mem_on = {
8474
[0] = PWRSTS_ON, /* aessmem */
8575
[1] = PWRSTS_ON, /* periphmem */
@@ -94,9 +84,6 @@ static struct powerdomain dss_7xx_pwrdm = {
9484
.prcm_partition = DRA7XX_PRM_PARTITION,
9585
.pwrsts = PWRSTS_OFF_ON,
9686
.banks = 1,
97-
.pwrsts_mem_ret = {
98-
[0] = PWRSTS_OFF_RET, /* dss_mem */
99-
},
10087
.pwrsts_mem_on = {
10188
[0] = PWRSTS_ON, /* dss_mem */
10289
},
@@ -110,10 +97,6 @@ static struct powerdomain l4per_7xx_pwrdm = {
11097
.prcm_partition = DRA7XX_PRM_PARTITION,
11198
.pwrsts = PWRSTS_ON,
11299
.banks = 2,
113-
.pwrsts_mem_ret = {
114-
[0] = PWRSTS_OFF_RET, /* nonretained_bank */
115-
[1] = PWRSTS_OFF_RET, /* retained_bank */
116-
},
117100
.pwrsts_mem_on = {
118101
[0] = PWRSTS_ON, /* nonretained_bank */
119102
[1] = PWRSTS_ON, /* retained_bank */
@@ -128,9 +111,6 @@ static struct powerdomain gpu_7xx_pwrdm = {
128111
.prcm_partition = DRA7XX_PRM_PARTITION,
129112
.pwrsts = PWRSTS_OFF_ON,
130113
.banks = 1,
131-
.pwrsts_mem_ret = {
132-
[0] = PWRSTS_OFF_RET, /* gpu_mem */
133-
},
134114
.pwrsts_mem_on = {
135115
[0] = PWRSTS_ON, /* gpu_mem */
136116
},
@@ -144,8 +124,6 @@ static struct powerdomain wkupaon_7xx_pwrdm = {
144124
.prcm_partition = DRA7XX_PRM_PARTITION,
145125
.pwrsts = PWRSTS_ON,
146126
.banks = 1,
147-
.pwrsts_mem_ret = {
148-
},
149127
.pwrsts_mem_on = {
150128
[0] = PWRSTS_ON, /* wkup_bank */
151129
},
@@ -158,13 +136,6 @@ static struct powerdomain core_7xx_pwrdm = {
158136
.prcm_partition = DRA7XX_PRM_PARTITION,
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.pwrsts = PWRSTS_ON,
160138
.banks = 5,
161-
.pwrsts_mem_ret = {
162-
[0] = PWRSTS_OFF_RET, /* core_nret_bank */
163-
[1] = PWRSTS_OFF_RET, /* core_ocmram */
164-
[2] = PWRSTS_OFF_RET, /* core_other_bank */
165-
[3] = PWRSTS_OFF_RET, /* ipu_l2ram */
166-
[4] = PWRSTS_OFF_RET, /* ipu_unicache */
167-
},
168139
.pwrsts_mem_on = {
169140
[0] = PWRSTS_ON, /* core_nret_bank */
170141
[1] = PWRSTS_ON, /* core_ocmram */
@@ -222,9 +193,6 @@ static struct powerdomain vpe_7xx_pwrdm = {
222193
.prcm_partition = DRA7XX_PRM_PARTITION,
223194
.pwrsts = PWRSTS_OFF_ON,
224195
.banks = 1,
225-
.pwrsts_mem_ret = {
226-
[0] = PWRSTS_OFF_RET, /* vpe_bank */
227-
},
228196
.pwrsts_mem_on = {
229197
[0] = PWRSTS_ON, /* vpe_bank */
230198
},
@@ -256,11 +224,6 @@ static struct powerdomain l3init_7xx_pwrdm = {
256224
.prcm_partition = DRA7XX_PRM_PARTITION,
257225
.pwrsts = PWRSTS_ON,
258226
.banks = 3,
259-
.pwrsts_mem_ret = {
260-
[0] = PWRSTS_OFF_RET, /* gmac_bank */
261-
[1] = PWRSTS_OFF_RET, /* l3init_bank1 */
262-
[2] = PWRSTS_OFF_RET, /* l3init_bank2 */
263-
},
264227
.pwrsts_mem_on = {
265228
[0] = PWRSTS_ON, /* gmac_bank */
266229
[1] = PWRSTS_ON, /* l3init_bank1 */
@@ -276,9 +239,6 @@ static struct powerdomain eve3_7xx_pwrdm = {
276239
.prcm_partition = DRA7XX_PRM_PARTITION,
277240
.pwrsts = PWRSTS_OFF_ON,
278241
.banks = 1,
279-
.pwrsts_mem_ret = {
280-
[0] = PWRSTS_OFF_RET, /* eve3_bank */
281-
},
282242
.pwrsts_mem_on = {
283243
[0] = PWRSTS_ON, /* eve3_bank */
284244
},
@@ -292,9 +252,6 @@ static struct powerdomain emu_7xx_pwrdm = {
292252
.prcm_partition = DRA7XX_PRM_PARTITION,
293253
.pwrsts = PWRSTS_OFF_ON,
294254
.banks = 1,
295-
.pwrsts_mem_ret = {
296-
[0] = PWRSTS_OFF_RET, /* emu_bank */
297-
},
298255
.pwrsts_mem_on = {
299256
[0] = PWRSTS_ON, /* emu_bank */
300257
},
@@ -307,11 +264,6 @@ static struct powerdomain dsp2_7xx_pwrdm = {
307264
.prcm_partition = DRA7XX_PRM_PARTITION,
308265
.pwrsts = PWRSTS_OFF_ON,
309266
.banks = 3,
310-
.pwrsts_mem_ret = {
311-
[0] = PWRSTS_OFF_RET, /* dsp2_edma */
312-
[1] = PWRSTS_OFF_RET, /* dsp2_l1 */
313-
[2] = PWRSTS_OFF_RET, /* dsp2_l2 */
314-
},
315267
.pwrsts_mem_on = {
316268
[0] = PWRSTS_ON, /* dsp2_edma */
317269
[1] = PWRSTS_ON, /* dsp2_l1 */
@@ -327,11 +279,6 @@ static struct powerdomain dsp1_7xx_pwrdm = {
327279
.prcm_partition = DRA7XX_PRM_PARTITION,
328280
.pwrsts = PWRSTS_OFF_ON,
329281
.banks = 3,
330-
.pwrsts_mem_ret = {
331-
[0] = PWRSTS_OFF_RET, /* dsp1_edma */
332-
[1] = PWRSTS_OFF_RET, /* dsp1_l1 */
333-
[2] = PWRSTS_OFF_RET, /* dsp1_l2 */
334-
},
335282
.pwrsts_mem_on = {
336283
[0] = PWRSTS_ON, /* dsp1_edma */
337284
[1] = PWRSTS_ON, /* dsp1_l1 */
@@ -347,9 +294,6 @@ static struct powerdomain cam_7xx_pwrdm = {
347294
.prcm_partition = DRA7XX_PRM_PARTITION,
348295
.pwrsts = PWRSTS_OFF_ON,
349296
.banks = 1,
350-
.pwrsts_mem_ret = {
351-
[0] = PWRSTS_OFF_RET, /* vip_bank */
352-
},
353297
.pwrsts_mem_on = {
354298
[0] = PWRSTS_ON, /* vip_bank */
355299
},
@@ -363,9 +307,6 @@ static struct powerdomain eve4_7xx_pwrdm = {
363307
.prcm_partition = DRA7XX_PRM_PARTITION,
364308
.pwrsts = PWRSTS_OFF_ON,
365309
.banks = 1,
366-
.pwrsts_mem_ret = {
367-
[0] = PWRSTS_OFF_RET, /* eve4_bank */
368-
},
369310
.pwrsts_mem_on = {
370311
[0] = PWRSTS_ON, /* eve4_bank */
371312
},
@@ -379,9 +320,6 @@ static struct powerdomain eve2_7xx_pwrdm = {
379320
.prcm_partition = DRA7XX_PRM_PARTITION,
380321
.pwrsts = PWRSTS_OFF_ON,
381322
.banks = 1,
382-
.pwrsts_mem_ret = {
383-
[0] = PWRSTS_OFF_RET, /* eve2_bank */
384-
},
385323
.pwrsts_mem_on = {
386324
[0] = PWRSTS_ON, /* eve2_bank */
387325
},
@@ -395,9 +333,6 @@ static struct powerdomain eve1_7xx_pwrdm = {
395333
.prcm_partition = DRA7XX_PRM_PARTITION,
396334
.pwrsts = PWRSTS_OFF_ON,
397335
.banks = 1,
398-
.pwrsts_mem_ret = {
399-
[0] = PWRSTS_OFF_RET, /* eve1_bank */
400-
},
401336
.pwrsts_mem_on = {
402337
[0] = PWRSTS_ON, /* eve1_bank */
403338
},

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