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virtuosoIngo Molnar
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perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it
Not all cores prevent using Intel PT and LBRs simultaneously, although most of them still do as of today. This patch adds an opt-in flag for such cores to disable mutual exclusivity between PT and LBR; also flip it on for Goldmont. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Arnaldo Carvalho de Melo <acme@infradead.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: vince@deater.net Link: http://lkml.kernel.org/r/1461857746-31346-4-git-send-email-alexander.shishkin@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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arch/x86/events/core.c

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@@ -360,6 +360,9 @@ int x86_add_exclusive(unsigned int what)
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{
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int i;
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if (x86_pmu.lbr_pt_coexist)
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return 0;
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if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
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mutex_lock(&pmc_reserve_mutex);
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for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
@@ -380,6 +383,9 @@ int x86_add_exclusive(unsigned int what)
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void x86_del_exclusive(unsigned int what)
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{
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if (x86_pmu.lbr_pt_coexist)
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return;
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atomic_dec(&x86_pmu.lbr_exclusive[what]);
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atomic_dec(&active_events);
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}

arch/x86/events/intel/core.c

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@@ -3609,6 +3609,7 @@ __init int intel_pmu_init(void)
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*/
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x86_pmu.pebs_aliases = NULL;
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x86_pmu.pebs_prec_dist = true;
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x86_pmu.lbr_pt_coexist = true;
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x86_pmu.flags |= PMU_FL_HAS_RSP_1;
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pr_cont("Goldmont events, ");
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break;

arch/x86/events/perf_event.h

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@@ -601,6 +601,7 @@ struct x86_pmu {
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u64 lbr_sel_mask; /* LBR_SELECT valid bits */
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const int *lbr_sel_map; /* lbr_select mappings */
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bool lbr_double_abort; /* duplicated lbr aborts */
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bool lbr_pt_coexist; /* LBR may coexist with PT */
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/*
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* Intel PT/LBR/BTS are exclusive

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