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clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLs
BugLink: https://bugs.launchpad.net/bugs/1918974 [ Upstream commit 292f75e ] All of the GPLLs in the MSM8998 Global Clock Controller are Fabia PLLs and not generic alphas: this was producing bad effects over the entire clock tree of MSM8998, where any GPLL child clock was declaring a false clock rate, due to their parent also showing the same. The issue resides in the calculation of the clock rate for the specific Alpha PLL type, where Fabia has a different register layout; switching the MSM8998 GPLLs to the correct Alpha Fabia PLL type fixes the rate (calculation) reading. While at it, also make these PLLs fixed since their rate is supposed to *never* be changed while the system runs, as this would surely crash the entire SoC. Now all the children of all the PLLs are also complying with their specified clock table and system stability is improved. Fixes: b5f5f52 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-7-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org> Signed-off-by: Kamal Mostafa <kamal@canonical.com> Signed-off-by: Kelsey Skunberg <kelsey.skunberg@canonical.com>
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‎drivers/clk/qcom/gcc-msm8998.c‎

Lines changed: 50 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -135,7 +135,7 @@ static struct pll_vco fabia_vco[] = {
135135

136136
static struct clk_alpha_pll gpll0 = {
137137
.offset = 0x0,
138-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
138+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
139139
.vco_table = fabia_vco,
140140
.num_vco = ARRAY_SIZE(fabia_vco),
141141
.clkr = {
@@ -145,58 +145,58 @@ static struct clk_alpha_pll gpll0 = {
145145
.name = "gpll0",
146146
.parent_names = (const char *[]){ "xo" },
147147
.num_parents = 1,
148-
.ops = &clk_alpha_pll_ops,
148+
.ops = &clk_alpha_pll_fixed_fabia_ops,
149149
}
150150
},
151151
};
152152

153153
static struct clk_alpha_pll_postdiv gpll0_out_even = {
154154
.offset = 0x0,
155-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
155+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
156156
.clkr.hw.init = &(struct clk_init_data){
157157
.name = "gpll0_out_even",
158158
.parent_names = (const char *[]){ "gpll0" },
159159
.num_parents = 1,
160-
.ops = &clk_alpha_pll_postdiv_ops,
160+
.ops = &clk_alpha_pll_postdiv_fabia_ops,
161161
},
162162
};
163163

164164
static struct clk_alpha_pll_postdiv gpll0_out_main = {
165165
.offset = 0x0,
166-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
166+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
167167
.clkr.hw.init = &(struct clk_init_data){
168168
.name = "gpll0_out_main",
169169
.parent_names = (const char *[]){ "gpll0" },
170170
.num_parents = 1,
171-
.ops = &clk_alpha_pll_postdiv_ops,
171+
.ops = &clk_alpha_pll_postdiv_fabia_ops,
172172
},
173173
};
174174

175175
static struct clk_alpha_pll_postdiv gpll0_out_odd = {
176176
.offset = 0x0,
177-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
177+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
178178
.clkr.hw.init = &(struct clk_init_data){
179179
.name = "gpll0_out_odd",
180180
.parent_names = (const char *[]){ "gpll0" },
181181
.num_parents = 1,
182-
.ops = &clk_alpha_pll_postdiv_ops,
182+
.ops = &clk_alpha_pll_postdiv_fabia_ops,
183183
},
184184
};
185185

186186
static struct clk_alpha_pll_postdiv gpll0_out_test = {
187187
.offset = 0x0,
188-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
188+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
189189
.clkr.hw.init = &(struct clk_init_data){
190190
.name = "gpll0_out_test",
191191
.parent_names = (const char *[]){ "gpll0" },
192192
.num_parents = 1,
193-
.ops = &clk_alpha_pll_postdiv_ops,
193+
.ops = &clk_alpha_pll_postdiv_fabia_ops,
194194
},
195195
};
196196

197197
static struct clk_alpha_pll gpll1 = {
198198
.offset = 0x1000,
199-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
199+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
200200
.vco_table = fabia_vco,
201201
.num_vco = ARRAY_SIZE(fabia_vco),
202202
.clkr = {
@@ -206,58 +206,58 @@ static struct clk_alpha_pll gpll1 = {
206206
.name = "gpll1",
207207
.parent_names = (const char *[]){ "xo" },
208208
.num_parents = 1,
209-
.ops = &clk_alpha_pll_ops,
209+
.ops = &clk_alpha_pll_fixed_fabia_ops,
210210
}
211211
},
212212
};
213213

214214
static struct clk_alpha_pll_postdiv gpll1_out_even = {
215215
.offset = 0x1000,
216-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
216+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
217217
.clkr.hw.init = &(struct clk_init_data){
218218
.name = "gpll1_out_even",
219219
.parent_names = (const char *[]){ "gpll1" },
220220
.num_parents = 1,
221-
.ops = &clk_alpha_pll_postdiv_ops,
221+
.ops = &clk_alpha_pll_postdiv_fabia_ops,
222222
},
223223
};
224224

225225
static struct clk_alpha_pll_postdiv gpll1_out_main = {
226226
.offset = 0x1000,
227-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
227+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
228228
.clkr.hw.init = &(struct clk_init_data){
229229
.name = "gpll1_out_main",
230230
.parent_names = (const char *[]){ "gpll1" },
231231
.num_parents = 1,
232-
.ops = &clk_alpha_pll_postdiv_ops,
232+
.ops = &clk_alpha_pll_postdiv_fabia_ops,
233233
},
234234
};
235235

236236
static struct clk_alpha_pll_postdiv gpll1_out_odd = {
237237
.offset = 0x1000,
238-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
238+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
239239
.clkr.hw.init = &(struct clk_init_data){
240240
.name = "gpll1_out_odd",
241241
.parent_names = (const char *[]){ "gpll1" },
242242
.num_parents = 1,
243-
.ops = &clk_alpha_pll_postdiv_ops,
243+
.ops = &clk_alpha_pll_postdiv_fabia_ops,
244244
},
245245
};
246246

247247
static struct clk_alpha_pll_postdiv gpll1_out_test = {
248248
.offset = 0x1000,
249-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
249+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
250250
.clkr.hw.init = &(struct clk_init_data){
251251
.name = "gpll1_out_test",
252252
.parent_names = (const char *[]){ "gpll1" },
253253
.num_parents = 1,
254-
.ops = &clk_alpha_pll_postdiv_ops,
254+
.ops = &clk_alpha_pll_postdiv_fabia_ops,
255255
},
256256
};
257257

258258
static struct clk_alpha_pll gpll2 = {
259259
.offset = 0x2000,
260-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
260+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
261261
.vco_table = fabia_vco,
262262
.num_vco = ARRAY_SIZE(fabia_vco),
263263
.clkr = {
@@ -267,58 +267,58 @@ static struct clk_alpha_pll gpll2 = {
267267
.name = "gpll2",
268268
.parent_names = (const char *[]){ "xo" },
269269
.num_parents = 1,
270-
.ops = &clk_alpha_pll_ops,
270+
.ops = &clk_alpha_pll_fixed_fabia_ops,
271271
}
272272
},
273273
};
274274

275275
static struct clk_alpha_pll_postdiv gpll2_out_even = {
276276
.offset = 0x2000,
277-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
277+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
278278
.clkr.hw.init = &(struct clk_init_data){
279279
.name = "gpll2_out_even",
280280
.parent_names = (const char *[]){ "gpll2" },
281281
.num_parents = 1,
282-
.ops = &clk_alpha_pll_postdiv_ops,
282+
.ops = &clk_alpha_pll_postdiv_fabia_ops,
283283
},
284284
};
285285

286286
static struct clk_alpha_pll_postdiv gpll2_out_main = {
287287
.offset = 0x2000,
288-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
288+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
289289
.clkr.hw.init = &(struct clk_init_data){
290290
.name = "gpll2_out_main",
291291
.parent_names = (const char *[]){ "gpll2" },
292292
.num_parents = 1,
293-
.ops = &clk_alpha_pll_postdiv_ops,
293+
.ops = &clk_alpha_pll_postdiv_fabia_ops,
294294
},
295295
};
296296

297297
static struct clk_alpha_pll_postdiv gpll2_out_odd = {
298298
.offset = 0x2000,
299-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
299+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
300300
.clkr.hw.init = &(struct clk_init_data){
301301
.name = "gpll2_out_odd",
302302
.parent_names = (const char *[]){ "gpll2" },
303303
.num_parents = 1,
304-
.ops = &clk_alpha_pll_postdiv_ops,
304+
.ops = &clk_alpha_pll_postdiv_fabia_ops,
305305
},
306306
};
307307

308308
static struct clk_alpha_pll_postdiv gpll2_out_test = {
309309
.offset = 0x2000,
310-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
310+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
311311
.clkr.hw.init = &(struct clk_init_data){
312312
.name = "gpll2_out_test",
313313
.parent_names = (const char *[]){ "gpll2" },
314314
.num_parents = 1,
315-
.ops = &clk_alpha_pll_postdiv_ops,
315+
.ops = &clk_alpha_pll_postdiv_fabia_ops,
316316
},
317317
};
318318

319319
static struct clk_alpha_pll gpll3 = {
320320
.offset = 0x3000,
321-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
321+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
322322
.vco_table = fabia_vco,
323323
.num_vco = ARRAY_SIZE(fabia_vco),
324324
.clkr = {
@@ -328,58 +328,58 @@ static struct clk_alpha_pll gpll3 = {
328328
.name = "gpll3",
329329
.parent_names = (const char *[]){ "xo" },
330330
.num_parents = 1,
331-
.ops = &clk_alpha_pll_ops,
331+
.ops = &clk_alpha_pll_fixed_fabia_ops,
332332
}
333333
},
334334
};
335335

336336
static struct clk_alpha_pll_postdiv gpll3_out_even = {
337337
.offset = 0x3000,
338-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
338+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
339339
.clkr.hw.init = &(struct clk_init_data){
340340
.name = "gpll3_out_even",
341341
.parent_names = (const char *[]){ "gpll3" },
342342
.num_parents = 1,
343-
.ops = &clk_alpha_pll_postdiv_ops,
343+
.ops = &clk_alpha_pll_postdiv_fabia_ops,
344344
},
345345
};
346346

347347
static struct clk_alpha_pll_postdiv gpll3_out_main = {
348348
.offset = 0x3000,
349-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
349+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
350350
.clkr.hw.init = &(struct clk_init_data){
351351
.name = "gpll3_out_main",
352352
.parent_names = (const char *[]){ "gpll3" },
353353
.num_parents = 1,
354-
.ops = &clk_alpha_pll_postdiv_ops,
354+
.ops = &clk_alpha_pll_postdiv_fabia_ops,
355355
},
356356
};
357357

358358
static struct clk_alpha_pll_postdiv gpll3_out_odd = {
359359
.offset = 0x3000,
360-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
360+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
361361
.clkr.hw.init = &(struct clk_init_data){
362362
.name = "gpll3_out_odd",
363363
.parent_names = (const char *[]){ "gpll3" },
364364
.num_parents = 1,
365-
.ops = &clk_alpha_pll_postdiv_ops,
365+
.ops = &clk_alpha_pll_postdiv_fabia_ops,
366366
},
367367
};
368368

369369
static struct clk_alpha_pll_postdiv gpll3_out_test = {
370370
.offset = 0x3000,
371-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
371+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
372372
.clkr.hw.init = &(struct clk_init_data){
373373
.name = "gpll3_out_test",
374374
.parent_names = (const char *[]){ "gpll3" },
375375
.num_parents = 1,
376-
.ops = &clk_alpha_pll_postdiv_ops,
376+
.ops = &clk_alpha_pll_postdiv_fabia_ops,
377377
},
378378
};
379379

380380
static struct clk_alpha_pll gpll4 = {
381381
.offset = 0x77000,
382-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
382+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
383383
.vco_table = fabia_vco,
384384
.num_vco = ARRAY_SIZE(fabia_vco),
385385
.clkr = {
@@ -389,52 +389,52 @@ static struct clk_alpha_pll gpll4 = {
389389
.name = "gpll4",
390390
.parent_names = (const char *[]){ "xo" },
391391
.num_parents = 1,
392-
.ops = &clk_alpha_pll_ops,
392+
.ops = &clk_alpha_pll_fixed_fabia_ops,
393393
}
394394
},
395395
};
396396

397397
static struct clk_alpha_pll_postdiv gpll4_out_even = {
398398
.offset = 0x77000,
399-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
399+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
400400
.clkr.hw.init = &(struct clk_init_data){
401401
.name = "gpll4_out_even",
402402
.parent_names = (const char *[]){ "gpll4" },
403403
.num_parents = 1,
404-
.ops = &clk_alpha_pll_postdiv_ops,
404+
.ops = &clk_alpha_pll_postdiv_fabia_ops,
405405
},
406406
};
407407

408408
static struct clk_alpha_pll_postdiv gpll4_out_main = {
409409
.offset = 0x77000,
410-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
410+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
411411
.clkr.hw.init = &(struct clk_init_data){
412412
.name = "gpll4_out_main",
413413
.parent_names = (const char *[]){ "gpll4" },
414414
.num_parents = 1,
415-
.ops = &clk_alpha_pll_postdiv_ops,
415+
.ops = &clk_alpha_pll_postdiv_fabia_ops,
416416
},
417417
};
418418

419419
static struct clk_alpha_pll_postdiv gpll4_out_odd = {
420420
.offset = 0x77000,
421-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
421+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
422422
.clkr.hw.init = &(struct clk_init_data){
423423
.name = "gpll4_out_odd",
424424
.parent_names = (const char *[]){ "gpll4" },
425425
.num_parents = 1,
426-
.ops = &clk_alpha_pll_postdiv_ops,
426+
.ops = &clk_alpha_pll_postdiv_fabia_ops,
427427
},
428428
};
429429

430430
static struct clk_alpha_pll_postdiv gpll4_out_test = {
431431
.offset = 0x77000,
432-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
432+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
433433
.clkr.hw.init = &(struct clk_init_data){
434434
.name = "gpll4_out_test",
435435
.parent_names = (const char *[]){ "gpll4" },
436436
.num_parents = 1,
437-
.ops = &clk_alpha_pll_postdiv_ops,
437+
.ops = &clk_alpha_pll_postdiv_fabia_ops,
438438
},
439439
};
440440

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