Architecture bindings?

[andreiw]

dma-coherent refers to "architectures which are by default non-coherent for I/O"
dma-noncoherent refers to "architectures which are by default coherent for I/O"

...but nothing in the DT spec spells out which architectures those might be. For example, the ACPI spec does talk about x86 being considered cache-coherent by default, and 32-bit Arm being considered non-cache-coherent by default.

In general, there is no section the spells out ISA implications for a device tree. Note that this would be different from "device bindings"...imho the ISA bindings totally make sense to be part of this document, but they ought to be in some document for sure. Curiously enough there's still PowerPC lingo in the DT spec - i.e. references to WIMG, e.g. in section on /memory node (with no definition of WIMG bit meaning... maybe this should be either made generic or updated to include another architecture as an example)

[robherring]

It is not really for the spec to decide what's the default for an arch and we try to keep architecture specifics out of it.

imho the ISA bindings totally make sense to be part of this document, but they ought to be in some document for sure.

Did you mean they should NOT be part of this doc? I'm not sure what you mean by ISA bindings? I assume that's CPU ISA, not ISA bus.

When moving ePAPR to the "DT Spec" we tried to remove PowerPCisms in the process. No doubt there are still some left. Patches welcome. :)

[andreiw]

Yeah I meant CPU ISA. I think my point is that the info needs to be somewhere (and I don't think it is anywhere at the moment). I don't know where I would look to answer the question of whether an architecture is or isn't by default cache coherent. Do you? Maybe it needs to be added somewhere in the DT bindings...I don't see it there.

Curiously qemu sets dma-coherent even on architectures where DMA is always coherent, like i386. Weird.