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mod.rs
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#![doc = "Peripheral access API for STM32F413 microcontrollers (generated using svd2rust v0.20.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.20.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
use core::marker::PhantomData;
use core::ops::Deref;
#[doc = r"Number available in the NVIC for configuring priority"]
pub const NVIC_PRIO_BITS: u8 = 4;
#[cfg(feature = "rt")]
pub use self::Interrupt as interrupt;
pub use cortex_m::peripheral::Peripherals as CorePeripherals;
pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU};
#[cfg(feature = "rt")]
pub use cortex_m_rt::interrupt;
#[cfg(feature = "rt")]
extern "C" {
fn PVD();
fn TAMP_STAMP();
fn RTC_WKUP();
fn FLASH();
fn RCC();
fn EXTI0();
fn EXTI1();
fn EXTI2();
fn EXTI3();
fn EXTI4();
fn DMA1_STREAM0();
fn DMA1_STREAM1();
fn DMA1_STREAM2();
fn DMA1_STREAM3();
fn DMA1_STREAM4();
fn DMA1_STREAM5();
fn DMA1_STREAM6();
fn ADC();
fn CAN1_TX();
fn CAN1_RX0();
fn CAN1_RX1();
fn CAN1_SCE();
fn EXTI9_5();
fn TIM1_BRK_TIM9();
fn TIM1_UP_TIM10();
fn TIM1_TRG_COM_TIM11();
fn TIM1_CC();
fn TIM2();
fn TIM3();
fn TIM4();
fn I2C1_EVT();
fn I2C1_ERR();
fn I2C2_EVT();
fn I2C2_ERR();
fn SPI1();
fn SPI2();
fn USART1();
fn USART2();
fn USART3();
fn EXTI15_10();
fn EXTI17_RTC_ALARM();
fn TIM8_BRK_TIM12();
fn TIM8_UP_TIM13();
fn TIM8_TRG_COM_TIM14();
fn TIM8_CC();
fn DMA1_STREAM7();
fn FSMC();
fn SDIO();
fn TIM5();
fn SPI3();
fn USART4();
fn UART5();
fn TIM6_GLB_IT_DAC1_DAC2();
fn TIM7();
fn DMA2_STREAM0();
fn DMA2_STREAM1();
fn DMA2_STREAM2();
fn DMA2_STREAM3();
fn DMA2_STREAM4();
fn DFSDM1_FLT0();
fn DFSDM1_FLT1();
fn CAN2_TX();
fn CAN2_RX0();
fn CAN2_RX1();
fn CAN2_SCE();
fn OTG_FS();
fn DMA2_STREAM5();
fn DMA2_STREAM6();
fn DMA2_STREAM7();
fn USART6();
fn I2C3_EV();
fn I2C3_ER();
fn CAN3_TX();
fn CAN3_RX0();
fn CAN3_RX1();
fn CAN3_SCE();
fn CRYPTO();
fn RNG();
fn FPU();
fn USART7();
fn USART8();
fn SPI4();
fn SPI5();
fn SAI1();
fn UART9();
fn UART10();
fn QUADSPI();
fn I2CFMP1EVENT();
fn I2CFMP1ERROR();
fn LPTIM1_OR_IT_EIT_23();
fn DFSDM2_FILTER1();
fn DFSDM2_FILTER2();
fn DFSDM2_FILTER3();
fn DFSDM2_FILTER4();
}
#[doc(hidden)]
pub union Vector {
_handler: unsafe extern "C" fn(),
_reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 102] = [
Vector { _reserved: 0 },
Vector { _handler: PVD },
Vector {
_handler: TAMP_STAMP,
},
Vector { _handler: RTC_WKUP },
Vector { _handler: FLASH },
Vector { _handler: RCC },
Vector { _handler: EXTI0 },
Vector { _handler: EXTI1 },
Vector { _handler: EXTI2 },
Vector { _handler: EXTI3 },
Vector { _handler: EXTI4 },
Vector {
_handler: DMA1_STREAM0,
},
Vector {
_handler: DMA1_STREAM1,
},
Vector {
_handler: DMA1_STREAM2,
},
Vector {
_handler: DMA1_STREAM3,
},
Vector {
_handler: DMA1_STREAM4,
},
Vector {
_handler: DMA1_STREAM5,
},
Vector {
_handler: DMA1_STREAM6,
},
Vector { _handler: ADC },
Vector { _handler: CAN1_TX },
Vector { _handler: CAN1_RX0 },
Vector { _handler: CAN1_RX1 },
Vector { _handler: CAN1_SCE },
Vector { _handler: EXTI9_5 },
Vector {
_handler: TIM1_BRK_TIM9,
},
Vector {
_handler: TIM1_UP_TIM10,
},
Vector {
_handler: TIM1_TRG_COM_TIM11,
},
Vector { _handler: TIM1_CC },
Vector { _handler: TIM2 },
Vector { _handler: TIM3 },
Vector { _handler: TIM4 },
Vector { _handler: I2C1_EVT },
Vector { _handler: I2C1_ERR },
Vector { _handler: I2C2_EVT },
Vector { _handler: I2C2_ERR },
Vector { _handler: SPI1 },
Vector { _handler: SPI2 },
Vector { _handler: USART1 },
Vector { _handler: USART2 },
Vector { _handler: USART3 },
Vector {
_handler: EXTI15_10,
},
Vector {
_handler: EXTI17_RTC_ALARM,
},
Vector { _reserved: 0 },
Vector {
_handler: TIM8_BRK_TIM12,
},
Vector {
_handler: TIM8_UP_TIM13,
},
Vector {
_handler: TIM8_TRG_COM_TIM14,
},
Vector { _handler: TIM8_CC },
Vector {
_handler: DMA1_STREAM7,
},
Vector { _handler: FSMC },
Vector { _handler: SDIO },
Vector { _handler: TIM5 },
Vector { _handler: SPI3 },
Vector { _handler: USART4 },
Vector { _handler: UART5 },
Vector {
_handler: TIM6_GLB_IT_DAC1_DAC2,
},
Vector { _handler: TIM7 },
Vector {
_handler: DMA2_STREAM0,
},
Vector {
_handler: DMA2_STREAM1,
},
Vector {
_handler: DMA2_STREAM2,
},
Vector {
_handler: DMA2_STREAM3,
},
Vector {
_handler: DMA2_STREAM4,
},
Vector {
_handler: DFSDM1_FLT0,
},
Vector {
_handler: DFSDM1_FLT1,
},
Vector { _handler: CAN2_TX },
Vector { _handler: CAN2_RX0 },
Vector { _handler: CAN2_RX1 },
Vector { _handler: CAN2_SCE },
Vector { _handler: OTG_FS },
Vector {
_handler: DMA2_STREAM5,
},
Vector {
_handler: DMA2_STREAM6,
},
Vector {
_handler: DMA2_STREAM7,
},
Vector { _handler: USART6 },
Vector { _handler: I2C3_EV },
Vector { _handler: I2C3_ER },
Vector { _handler: CAN3_TX },
Vector { _handler: CAN3_RX0 },
Vector { _handler: CAN3_RX1 },
Vector { _handler: CAN3_SCE },
Vector { _reserved: 0 },
Vector { _handler: CRYPTO },
Vector { _handler: RNG },
Vector { _handler: FPU },
Vector { _handler: USART7 },
Vector { _handler: USART8 },
Vector { _handler: SPI4 },
Vector { _handler: SPI5 },
Vector { _reserved: 0 },
Vector { _handler: SAI1 },
Vector { _handler: UART9 },
Vector { _handler: UART10 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: QUADSPI },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector {
_handler: I2CFMP1EVENT,
},
Vector {
_handler: I2CFMP1ERROR,
},
Vector {
_handler: LPTIM1_OR_IT_EIT_23,
},
Vector {
_handler: DFSDM2_FILTER1,
},
Vector {
_handler: DFSDM2_FILTER2,
},
Vector {
_handler: DFSDM2_FILTER3,
},
Vector {
_handler: DFSDM2_FILTER4,
},
];
#[doc = r"Enumeration of all the interrupts."]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
#[doc = "1 - PVD through EXTI line detection interrupt"]
PVD = 1,
#[doc = "2 - Tamper and TimeStamp interrupts through the EXTI line"]
TAMP_STAMP = 2,
#[doc = "3 - RTC Wakeup interrupt through the EXTI line"]
RTC_WKUP = 3,
#[doc = "4 - FLASH global interrupt"]
FLASH = 4,
#[doc = "5 - RCC global interrupt"]
RCC = 5,
#[doc = "6 - EXTI Line0 interrupt"]
EXTI0 = 6,
#[doc = "7 - EXTI Line1 interrupt"]
EXTI1 = 7,
#[doc = "8 - EXTI Line2 interrupt"]
EXTI2 = 8,
#[doc = "9 - EXTI Line3 interrupt"]
EXTI3 = 9,
#[doc = "10 - EXTI Line4 interrupt"]
EXTI4 = 10,
#[doc = "11 - DMA1 Stream0 global interrupt"]
DMA1_STREAM0 = 11,
#[doc = "12 - DMA1 Stream1 global interrupt"]
DMA1_STREAM1 = 12,
#[doc = "13 - DMA1 Stream2 global interrupt"]
DMA1_STREAM2 = 13,
#[doc = "14 - DMA1 Stream3 global interrupt"]
DMA1_STREAM3 = 14,
#[doc = "15 - DMA1 Stream4 global interrupt"]
DMA1_STREAM4 = 15,
#[doc = "16 - DMA1 Stream5 global interrupt"]
DMA1_STREAM5 = 16,
#[doc = "17 - DMA1 Stream6 global interrupt"]
DMA1_STREAM6 = 17,
#[doc = "18 - ADC1 global interrupt"]
ADC = 18,
#[doc = "19 - CAN1 TX interrupts"]
CAN1_TX = 19,
#[doc = "20 - CAN1 RX0 interrupts"]
CAN1_RX0 = 20,
#[doc = "21 - CAN1 RX1 interrupts"]
CAN1_RX1 = 21,
#[doc = "22 - CAN1 SCE interrupt"]
CAN1_SCE = 22,
#[doc = "23 - EXTI Line\\[9:5\\]
interrupts"]
EXTI9_5 = 23,
#[doc = "24 - TIM1 Break interrupt and TIM9 global interrupt"]
TIM1_BRK_TIM9 = 24,
#[doc = "25 - TIM1 Update interrupt and TIM10 global interrupt"]
TIM1_UP_TIM10 = 25,
#[doc = "26 - TIM1 Trigger and Commutation interrupts and TIM11 global interrupt"]
TIM1_TRG_COM_TIM11 = 26,
#[doc = "27 - TIM1 Capture Compare interrupt"]
TIM1_CC = 27,
#[doc = "28 - TIM2 global interrupt"]
TIM2 = 28,
#[doc = "29 - TIM3 global interrupt"]
TIM3 = 29,
#[doc = "30 - TIM4 global interrupt"]
TIM4 = 30,
#[doc = "31 - I2C1 event interrupt"]
I2C1_EVT = 31,
#[doc = "32 - I2C1 error interrupt"]
I2C1_ERR = 32,
#[doc = "33 - I2C2 event interrupt"]
I2C2_EVT = 33,
#[doc = "34 - I2C2 error interrupt"]
I2C2_ERR = 34,
#[doc = "35 - SPI1 global interrupt"]
SPI1 = 35,
#[doc = "36 - SPI2 global interrupt"]
SPI2 = 36,
#[doc = "37 - USART1 global interrupt"]
USART1 = 37,
#[doc = "38 - USART2 global interrupt"]
USART2 = 38,
#[doc = "39 - USART3 global interrupt"]
USART3 = 39,
#[doc = "40 - EXTI Line\\[15:10\\]
interrupts"]
EXTI15_10 = 40,
#[doc = "41 - RTC Alarms (A and B) through EXTI line interrupt"]
EXTI17_RTC_ALARM = 41,
#[doc = "43 - Timer 12 global interrupt"]
TIM8_BRK_TIM12 = 43,
#[doc = "44 - Timer 13 global interrupt"]
TIM8_UP_TIM13 = 44,
#[doc = "45 - Timer 14 global interrupt"]
TIM8_TRG_COM_TIM14 = 45,
#[doc = "46 - TIM8 Cap/Com interrupt"]
TIM8_CC = 46,
#[doc = "47 - DMA1 global interrupt Channel 7"]
DMA1_STREAM7 = 47,
#[doc = "48 - FSMC global interrupt"]
FSMC = 48,
#[doc = "49 - SDIO global interrupt"]
SDIO = 49,
#[doc = "50 - TIM5 global interrupt"]
TIM5 = 50,
#[doc = "51 - SPI3 global interrupt"]
SPI3 = 51,
#[doc = "52 - UART 4 global interrupt"]
USART4 = 52,
#[doc = "53 - UART 5global interrupt"]
UART5 = 53,
#[doc = "54 - TIM6 global and DAC12 underrun interrupts"]
TIM6_GLB_IT_DAC1_DAC2 = 54,
#[doc = "55 - TIM7 global interrupt"]
TIM7 = 55,
#[doc = "56 - DMA2 Stream0 global interrupt"]
DMA2_STREAM0 = 56,
#[doc = "57 - DMA2 Stream1 global interrupt"]
DMA2_STREAM1 = 57,
#[doc = "58 - DMA2 Stream2 global interrupt"]
DMA2_STREAM2 = 58,
#[doc = "59 - DMA2 Stream3 global interrupt"]
DMA2_STREAM3 = 59,
#[doc = "60 - DMA2 Stream4 global interrupt"]
DMA2_STREAM4 = 60,
#[doc = "61 - SD filter0 global interrupt"]
DFSDM1_FLT0 = 61,
#[doc = "62 - SD filter1 global interrupt"]
DFSDM1_FLT1 = 62,
#[doc = "63 - CAN2 TX interrupt"]
CAN2_TX = 63,
#[doc = "64 - BXCAN2 RX0 interrupt"]
CAN2_RX0 = 64,
#[doc = "65 - BXCAN2 RX1 interrupt"]
CAN2_RX1 = 65,
#[doc = "66 - CAN2 SCE interrupt"]
CAN2_SCE = 66,
#[doc = "67 - USB OTG FS Interrupt"]
OTG_FS = 67,
#[doc = "68 - DMA2 Stream5 global interrupt"]
DMA2_STREAM5 = 68,
#[doc = "69 - DMA2 Stream6 global interrupt"]
DMA2_STREAM6 = 69,
#[doc = "70 - DMA2 Stream7 global interrupt"]
DMA2_STREAM7 = 70,
#[doc = "71 - USART6 global interrupt"]
USART6 = 71,
#[doc = "72 - I2C3 event interrupt"]
I2C3_EV = 72,
#[doc = "73 - I2C3 error interrupt"]
I2C3_ER = 73,
#[doc = "74 - CAN 3 TX interrupt"]
CAN3_TX = 74,
#[doc = "75 - BxCAN 3 RX0 interrupt"]
CAN3_RX0 = 75,
#[doc = "76 - BxCAN 3 RX1 interrupt"]
CAN3_RX1 = 76,
#[doc = "77 - CAN 3 SCE interrupt"]
CAN3_SCE = 77,
#[doc = "79 - AES global interrupt"]
CRYPTO = 79,
#[doc = "80 - Rng global interrupt"]
RNG = 80,
#[doc = "81 - Floating point unit"]
FPU = 81,
#[doc = "82 - USART7 global interrupt"]
USART7 = 82,
#[doc = "83 - USART8 global interrupt"]
USART8 = 83,
#[doc = "84 - SPI4 global interrupt"]
SPI4 = 84,
#[doc = "85 - SPI5 global interrupt"]
SPI5 = 85,
#[doc = "87 - SAI1 global interrupt"]
SAI1 = 87,
#[doc = "88 - UART9 global interrupt"]
UART9 = 88,
#[doc = "89 - UART10 global interrupt"]
UART10 = 89,
#[doc = "92 - Quad-SPI global interrupt"]
QUADSPI = 92,
#[doc = "95 - I2CFMP1 event interrupt"]
I2CFMP1EVENT = 95,
#[doc = "96 - I2CFMP1 error interrupt"]
I2CFMP1ERROR = 96,
#[doc = "97 - LP Timer global interrupt or EXT1 interrupt line 23"]
LPTIM1_OR_IT_EIT_23 = 97,
#[doc = "98 - DFSDM2 SD filter 1 global interrupt"]
DFSDM2_FILTER1 = 98,
#[doc = "99 - DFSDM2 SD filter 2 global interrupt"]
DFSDM2_FILTER2 = 99,
#[doc = "100 - DFSDM2 SD filter 3 global interrupt"]
DFSDM2_FILTER3 = 100,
#[doc = "101 - DFSDM2 SD filter 4 global interrupt"]
DFSDM2_FILTER4 = 101,
}
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
#[inline(always)]
fn number(self) -> u16 {
self as u16
}
}
#[doc = "Advanced encryption standard hardware accelerator"]
pub struct AES {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for AES {}
impl AES {
#[doc = r"Pointer to the register block"]
pub const PTR: *const aes::RegisterBlock = 0x5006_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const aes::RegisterBlock {
Self::PTR
}
}
impl Deref for AES {
type Target = aes::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for AES {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("AES").finish()
}
}
#[doc = "Advanced encryption standard hardware accelerator"]
pub mod aes;
#[doc = "Advanced-timers"]
pub struct TIM1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for TIM1 {}
impl TIM1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const tim1::RegisterBlock = 0x4001_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const tim1::RegisterBlock {
Self::PTR
}
}
impl Deref for TIM1 {
type Target = tim1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for TIM1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM1").finish()
}
}
#[doc = "Advanced-timers"]
pub mod tim1;
#[doc = "Advanced-timers"]
pub struct TIM8 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for TIM8 {}
impl TIM8 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const tim1::RegisterBlock = 0x4001_0400 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const tim1::RegisterBlock {
Self::PTR
}
}
impl Deref for TIM8 {
type Target = tim1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for TIM8 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM8").finish()
}
}
#[doc = "Advanced-timers"]
pub use tim1 as tim8;
#[doc = "Analog-to-digital converter"]
pub struct ADC1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for ADC1 {}
impl ADC1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const adc1::RegisterBlock = 0x4001_2000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const adc1::RegisterBlock {
Self::PTR
}
}
impl Deref for ADC1 {
type Target = adc1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for ADC1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ADC1").finish()
}
}
#[doc = "Analog-to-digital converter"]
pub mod adc1;
#[doc = "Basic timers"]
pub struct TIM7 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for TIM7 {}
impl TIM7 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const tim7::RegisterBlock = 0x4000_1400 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const tim7::RegisterBlock {
Self::PTR
}
}
impl Deref for TIM7 {
type Target = tim7::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for TIM7 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM7").finish()
}
}
#[doc = "Basic timers"]
pub mod tim7;
#[doc = "Basic timers"]
pub struct TIM6 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for TIM6 {}
impl TIM6 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const tim7::RegisterBlock = 0x4000_1000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const tim7::RegisterBlock {
Self::PTR
}
}
impl Deref for TIM6 {
type Target = tim7::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for TIM6 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM6").finish()
}
}
#[doc = "Basic timers"]
pub use tim7 as tim6;
#[doc = "Controller area network"]
pub struct CAN1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for CAN1 {}
impl CAN1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const can1::RegisterBlock = 0x4000_6400 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const can1::RegisterBlock {
Self::PTR
}
}
impl Deref for CAN1 {
type Target = can1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for CAN1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CAN1").finish()
}
}
#[doc = "Controller area network"]
pub mod can1;
#[doc = "Controller area network"]
pub struct CAN2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for CAN2 {}
impl CAN2 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const can1::RegisterBlock = 0x4000_6800 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const can1::RegisterBlock {
Self::PTR
}
}
impl Deref for CAN2 {
type Target = can1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for CAN2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CAN2").finish()
}
}
#[doc = "Controller area network"]
pub use can1 as can2;
#[doc = "Controller area network"]
pub struct CAN3 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for CAN3 {}
impl CAN3 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const can1::RegisterBlock = 0x4000_6c00 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const can1::RegisterBlock {
Self::PTR
}
}
impl Deref for CAN3 {
type Target = can1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for CAN3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CAN3").finish()
}
}
#[doc = "Controller area network"]
pub use can1 as can3;
#[doc = "Cryptographic processor"]
pub struct CRC {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for CRC {}
impl CRC {
#[doc = r"Pointer to the register block"]
pub const PTR: *const crc::RegisterBlock = 0x4002_3000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const crc::RegisterBlock {
Self::PTR
}
}
impl Deref for CRC {
type Target = crc::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for CRC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CRC").finish()
}
}
#[doc = "Cryptographic processor"]
pub mod crc;
#[doc = "Debug support"]
pub struct DBGMCU {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for DBGMCU {}
impl DBGMCU {
#[doc = r"Pointer to the register block"]
pub const PTR: *const dbgmcu::RegisterBlock = 0xe004_2000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const dbgmcu::RegisterBlock {
Self::PTR
}
}
impl Deref for DBGMCU {
type Target = dbgmcu::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for DBGMCU {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DBGMCU").finish()
}
}
#[doc = "Debug support"]
pub mod dbgmcu;
#[doc = "Digital filter for sigma delta modulators"]
pub struct DFSDM2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for DFSDM2 {}
impl DFSDM2 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const dfsdm2::RegisterBlock = 0x4001_6400 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const dfsdm2::RegisterBlock {
Self::PTR
}
}
impl Deref for DFSDM2 {
type Target = dfsdm2::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for DFSDM2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DFSDM2").finish()
}
}
#[doc = "Digital filter for sigma delta modulators"]
pub mod dfsdm2;
#[doc = "Digital filter for sigma delta modulators"]
pub struct DFSDM1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for DFSDM1 {}
impl DFSDM1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const dfsdm2::RegisterBlock = 0x4001_6000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const dfsdm2::RegisterBlock {
Self::PTR
}
}
impl Deref for DFSDM1 {
type Target = dfsdm2::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for DFSDM1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DFSDM1").finish()
}
}
#[doc = "Digital filter for sigma delta modulators"]
pub use dfsdm2 as dfsdm1;
#[doc = "Digital-to-analog converter"]
pub struct DAC {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for DAC {}
impl DAC {
#[doc = r"Pointer to the register block"]
pub const PTR: *const dac::RegisterBlock = 0x4000_7400 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const dac::RegisterBlock {
Self::PTR
}
}
impl Deref for DAC {
type Target = dac::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for DAC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DAC").finish()
}
}
#[doc = "Digital-to-analog converter"]
pub mod dac;
#[doc = "DMA controller"]
pub struct DMA1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for DMA1 {}
impl DMA1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const dma1::RegisterBlock = 0x4002_6000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const dma1::RegisterBlock {
Self::PTR
}
}
impl Deref for DMA1 {
type Target = dma1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for DMA1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DMA1").finish()
}
}
#[doc = "DMA controller"]
pub mod dma1;
#[doc = "DMA controller"]
pub struct DMA2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for DMA2 {}
impl DMA2 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const dma1::RegisterBlock = 0x4002_6400 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const dma1::RegisterBlock {
Self::PTR
}
}
impl Deref for DMA2 {
type Target = dma1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for DMA2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DMA2").finish()
}
}
#[doc = "DMA controller"]
pub use dma1 as dma2;
#[doc = "External interrupt/event controller"]
pub struct EXTI {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for EXTI {}
impl EXTI {
#[doc = r"Pointer to the register block"]
pub const PTR: *const exti::RegisterBlock = 0x4001_3c00 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const exti::RegisterBlock {
Self::PTR
}
}
impl Deref for EXTI {
type Target = exti::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for EXTI {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("EXTI").finish()
}
}
#[doc = "External interrupt/event controller"]
pub mod exti;
#[doc = "fast-mode Inter-integrated circuit"]
pub struct FMPI2C1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for FMPI2C1 {}
impl FMPI2C1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const fmpi2c1::RegisterBlock = 0x4000_6000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const fmpi2c1::RegisterBlock {
Self::PTR
}
}
impl Deref for FMPI2C1 {
type Target = fmpi2c1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for FMPI2C1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FMPI2C1").finish()
}
}
#[doc = "fast-mode Inter-integrated circuit"]
pub mod fmpi2c1;
#[doc = "FLASH"]
pub struct FLASH {
_marker: PhantomData<*const ()>,