testbench.txt

-- Test bench, VHDL 93 style
-- Automaticall generated by a Pyhton Script 
-- (c) Dilawar Singh, 2011
-- dilawawr@ee.iitb.ac.in

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.<entity>

entity tb_<entity> is

end entity tb_<entity>;

 

architecture stimulus of tb_<entity> is
    component <component> is

       port (
                    <ports>
        );

    end component fib;

 

    function str_to_stdvec(inp: string) return std_ulogic_vector is

        variable temp: std_ulogic_vector(inp'range) := (others => 'X');

    begin

        for i in inp'range loop

            if (inp(i) = '1') then

                temp(i) := '1';

            elsif (inp(i) = '0') then

                temp(i) := '0';

            end if;

        end loop;

        return temp;

    end function str_to_stdvec;

 

    function stdvec_to_str(inp: std_ulogic_vector) return string is

        variable temp: string(inp'left+1 downto 1) := (others => 'X');

    begin

        for i in inp'reverse_range loop

            if (inp(i) = '1') then

                temp(i+1) := '1';

            elsif (inp(i) = '0') then

                temp(i+1) := '0';

            end if;

        end loop;

        return temp;

    end function stdvec_to_str;

 

    signal Clk,Clr: std_ulogic;

    signal Load: std_ulogic;

    signal Data_in: std_ulogic_vector(15 downto 0);

    signal S: std_ulogic_vector(15 downto 0);

    signal done: std_ulogic := '0';

 

    constant PERIOD: time := 50 ns;

 

begin

    UUT: fib port map(Clk=>Clk,Clr=>Clr,Load=>Load,

                      Data_in=>Data_in,S=>S);

 

    Clock: process

        variable c: std_ulogic := '0';

    begin

        while (done = '0') loop

            wait for PERIOD/2;

            c := not c;

            Clk <= c;

        end loop;

    end process Clock;  

 

    Read_input: process  

        file vector_file: text;

 

        variable stimulus_in: std_ulogic_vector(33 downto 0);

        variable S_expected: std_ulogic_vector(15 downto 0);

        variable str_stimulus_in: string(34 downto 1);

        variable err_cnt: integer := 0;

        variable file_line: line;

 

    begin

 

        file_open(vector_file,"tfib93.vec",READ_MODE);

 

        wait until rising_edge(Clk);

 

        while not endfile(vector_file) loop

            readline (vector_file,file_line);

            read (file_line,str_stimulus_in) ;

            assert (false)

                report "Vector: " & str_stimulus_in

                severity note;

            stimulus_in := str_to_stdvec (str_stimulus_in);

 

            wait for 1 ns;

 

            --Get input side of vector...

            Clr <= stimulus_in(33);

            Load <= stimulus_in(32);

            Data_in <= stimulus_in(31 downto 16);

 

            --Put output side (expected values) into a variable...

            S_expected := stimulus_in(15 downto 0);

 

            wait until falling_edge(Clk);

 

            -- Check the expected value against the results...

            if (S /= S_expected) then

                err_cnt := err_cnt + 1;

                assert false

                    report "Vector failure!" & lf &

                    "Expected S to be  " & stdvec_to_str(S_expected) & lf &

                    "but its value was " & stdvec_to_str(S) & lf

                    severity note;

            end if;

        end loop;

 

        file_close(vector_file);

 

        done <= '1';

 

        if (err_cnt = 0) then

            assert false

                report "No errors." & lf & lf

                severity note;

        else

            assert false

                report "There were errors in the test." & lf

                severity note;

        end if;

        wait;

 

    end process Read_input;

end architecture stimulus;

 

-- Add a configuration statement. This statement actually states the

-- default configuration, and so it is optional.

configuration build1 of testfib is

    for stimulus

        for DUT: fib use entity work.fib(behavior)

            port map(Clk=>Clk,Clr=>Clr,Load=>Load,

                      Data_in=>Data_in,S=>S);

        end for;

    end for;

end configuration build1;