Implement more AVX/AVX2 intrinsics

Author: FeiPengIntel

src/jit/emitxarch.cpp

@@ -224,6 +224,9 @@ bool emitter::IsDstDstSrcAVXInstruction(instruction ins)
         case INS_vinsertf128:
         case INS_vinserti128:
         case INS_vperm2i128:
+        case INS_vperm2f128:
+        case INS_vpermilpsvar:
+        case INS_vpermilpdvar:
         case INS_vpsrlvd:
         case INS_vpsrlvq:
         case INS_vpsravd:
@@ -324,6 +327,7 @@ bool emitter::TakesVexPrefix(instruction ins)
         case INS_prefetcht2:
         case INS_sfence:
         case INS_vzeroupper:
+        case INS_vzeroall:
             return false;
         default:
             break;
@@ -2556,7 +2560,8 @@ void emitter::emitIns(instruction ins)
                            ins == INS_sahf || ins == INS_stosb || ins == INS_stosd || ins == INS_stosp
 #ifndef LEGACY_BACKEND
                            // These instructions take zero operands
-                           || ins == INS_vzeroupper || ins == INS_lfence || ins == INS_mfence || ins == INS_sfence
+                           || ins == INS_vzeroupper || ins == INS_vzeroall || ins == INS_lfence || ins == INS_mfence ||
+                           ins == INS_sfence
 #endif
                            );
 
@@ -2585,7 +2590,7 @@ void emitter::emitIns(instruction ins)
 
 #ifndef LEGACY_BACKEND
     // vzeroupper includes its 2-byte VEX prefix in its MR code.
-    assert((ins != INS_vzeroupper) || (sz == 3));
+    assert((ins != INS_vzeroupper) || (ins != INS_vzeroall) || (sz == 3));
 #endif
 
     insFormat fmt = IF_NONE;
@@ -4299,9 +4304,9 @@ void emitter::emitIns_R_R_C(
 }
 
 /*****************************************************************************
-*
-*  Add an instruction with three register operands.
-*/
+ *
+ *  Add an instruction with three register operands.
+ */
 
 void emitter::emitIns_R_R_R(instruction ins, emitAttr attr, regNumber targetReg, regNumber reg1, regNumber reg2)
 {
@@ -4423,16 +4428,16 @@ void emitter::emitIns_R_R_C_I(
 }
 
 /**********************************************************************************
-* emitIns_R_R_R_I: Add an instruction with three register operands and an immediate.
-*
-* Arguments:
-*    ins       - the instruction to add
-*    attr      - the emitter attribute for instruction
-*    targetReg - the target (destination) register
-*    reg1      - the first source register
-*    reg2      - the second source register
-*    ival      - the immediate value
-*/
+ * emitIns_R_R_R_I: Add an instruction with three register operands and an immediate.
+ *
+ * Arguments:
+ *    ins       - the instruction to add
+ *    attr      - the emitter attribute for instruction
+ *    targetReg - the target (destination) register
+ *    reg1      - the first source register
+ *    reg2      - the second source register
+ *    ival      - the immediate value
+ */
 
 void emitter::emitIns_R_R_R_I(
     instruction ins, emitAttr attr, regNumber targetReg, regNumber reg1, regNumber reg2, int ival)

src/jit/hwintrinsiccodegenxarch.cpp

@@ -1318,7 +1318,7 @@ void CodeGen::genAvxOrAvx2Intrinsic(GenTreeHWIntrinsic* node)
             // to ensure that Bits MAXVL-1:128 are zeroed.
 
             assert(op2 == nullptr);
-            regNumber op1Reg = op1->gtRegNum;
+            regNumber   op1Reg = op1->gtRegNum;
             emit->emitIns_R_R(ins, emitTypeSize(TYP_SIMD16), targetReg, op1Reg);
             break;
         }
@@ -1331,7 +1331,6 @@ void CodeGen::genAvxOrAvx2Intrinsic(GenTreeHWIntrinsic* node)
 
             if (op1Reg != targetReg)
             {
-                instruction ins = Compiler::insOfHWIntrinsic(intrinsicID, node->gtSIMDBaseType);
                 emit->emitIns_R_R(ins, emitTypeSize(TYP_SIMD32), targetReg, op1Reg);
             }
             break;