Skip to content
This repository was archived by the owner on Jan 23, 2023. It is now read-only.

Commit cfba1f8

Browse files
FeiPengIntelFeiPengIntel
committed
table drive Intel hardware intrinsic
1 parent cab0db6 commit cfba1f8

24 files changed

+1113
-346
lines changed

‎src/jit/codegenlinear.h

+1
Original file line numberDiff line numberDiff line change
@@ -131,6 +131,7 @@ void genFMAIntrinsic(GenTreeHWIntrinsic* node);
131131
void genLZCNTIntrinsic(GenTreeHWIntrinsic* node);
132132
void genPCLMULQDQIntrinsic(GenTreeHWIntrinsic* node);
133133
void genPOPCNTIntrinsic(GenTreeHWIntrinsic* node);
134+
bool genTableDrivableHWIntrinsic(HWIntrinsicCategory category);
134135
#endif // FEATURE_HW_INTRINSICS
135136

136137
#if !defined(_TARGET_64BIT_)

‎src/jit/compiler.h

+27-63
Original file line numberDiff line numberDiff line change
@@ -2058,9 +2058,13 @@ class Compiler
20582058

20592059
#if FEATURE_HW_INTRINSICS
20602060
GenTreeHWIntrinsic* gtNewSimdHWIntrinsicNode(
2061-
var_types type, GenTree* op1, NamedIntrinsic hwIntrinsicID, var_types baseType, unsigned size);
2062-
GenTreeHWIntrinsic* gtNewSimdHWIntrinsicNode(
2063-
var_types type, GenTree* op1, GenTree* op2, NamedIntrinsic hwIntrinsicID, var_types baseType, unsigned size);
2061+
var_types type, GenTree* op1, NamedIntrinsic hwIntrinsicID, var_types baseType, unsigned simdSize);
2062+
GenTreeHWIntrinsic* gtNewSimdHWIntrinsicNode(var_types type,
2063+
GenTree* op1,
2064+
GenTree* op2,
2065+
NamedIntrinsic hwIntrinsicID,
2066+
var_types baseType,
2067+
unsigned simdSize);
20642068
GenTreeHWIntrinsic* gtNewScalarHWIntrinsicNode(var_types type, GenTree* op1, NamedIntrinsic hwIntrinsicID);
20652069
GenTreeHWIntrinsic* gtNewScalarHWIntrinsicNode(var_types type,
20662070
GenTree* op1,
@@ -3036,68 +3040,28 @@ class Compiler
30363040
CORINFO_METHOD_HANDLE method,
30373041
CORINFO_SIG_INFO* sig,
30383042
bool mustExpand);
3039-
GenTree* impSSEIntrinsic(NamedIntrinsic intrinsic,
3040-
CORINFO_METHOD_HANDLE method,
3041-
CORINFO_SIG_INFO* sig,
3042-
bool mustExpand);
3043-
GenTree* impSSE2Intrinsic(NamedIntrinsic intrinsic,
3044-
CORINFO_METHOD_HANDLE method,
3045-
CORINFO_SIG_INFO* sig,
3046-
bool mustExpand);
3047-
GenTree* impSSE3Intrinsic(NamedIntrinsic intrinsic,
3048-
CORINFO_METHOD_HANDLE method,
3049-
CORINFO_SIG_INFO* sig,
3050-
bool mustExpand);
3051-
GenTree* impSSSE3Intrinsic(NamedIntrinsic intrinsic,
3052-
CORINFO_METHOD_HANDLE method,
3053-
CORINFO_SIG_INFO* sig,
3054-
bool mustExpand);
3055-
GenTree* impSSE41Intrinsic(NamedIntrinsic intrinsic,
3056-
CORINFO_METHOD_HANDLE method,
3057-
CORINFO_SIG_INFO* sig,
3058-
bool mustExpand);
3059-
GenTree* impSSE42Intrinsic(NamedIntrinsic intrinsic,
3060-
CORINFO_METHOD_HANDLE method,
3061-
CORINFO_SIG_INFO* sig,
3062-
bool mustExpand);
3063-
GenTree* impAVXIntrinsic(NamedIntrinsic intrinsic,
3064-
CORINFO_METHOD_HANDLE method,
3065-
CORINFO_SIG_INFO* sig,
3066-
bool mustExpand);
3067-
GenTree* impAVX2Intrinsic(NamedIntrinsic intrinsic,
3068-
CORINFO_METHOD_HANDLE method,
3069-
CORINFO_SIG_INFO* sig,
3070-
bool mustExpand);
3071-
GenTree* impAESIntrinsic(NamedIntrinsic intrinsic,
3072-
CORINFO_METHOD_HANDLE method,
3073-
CORINFO_SIG_INFO* sig,
3074-
bool mustExpand);
3075-
GenTree* impBMI1Intrinsic(NamedIntrinsic intrinsic,
3076-
CORINFO_METHOD_HANDLE method,
3077-
CORINFO_SIG_INFO* sig,
3078-
bool mustExpand);
3079-
GenTree* impBMI2Intrinsic(NamedIntrinsic intrinsic,
3080-
CORINFO_METHOD_HANDLE method,
3081-
CORINFO_SIG_INFO* sig,
3082-
bool mustExpand);
3083-
GenTree* impFMAIntrinsic(NamedIntrinsic intrinsic,
3084-
CORINFO_METHOD_HANDLE method,
3085-
CORINFO_SIG_INFO* sig,
3086-
bool mustExpand);
3087-
GenTree* impLZCNTIntrinsic(NamedIntrinsic intrinsic,
3088-
CORINFO_METHOD_HANDLE method,
3089-
CORINFO_SIG_INFO* sig,
3090-
bool mustExpand);
3091-
GenTree* impPCLMULQDQIntrinsic(NamedIntrinsic intrinsic,
3092-
CORINFO_METHOD_HANDLE method,
3093-
CORINFO_SIG_INFO* sig,
3094-
bool mustExpand);
3095-
GenTree* impPOPCNTIntrinsic(NamedIntrinsic intrinsic,
3096-
CORINFO_METHOD_HANDLE method,
3097-
CORINFO_SIG_INFO* sig,
3098-
bool mustExpand);
3043+
GenTree* impSSEIntrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);
3044+
GenTree* impSSE2Intrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);
3045+
GenTree* impSSE3Intrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);
3046+
GenTree* impSSSE3Intrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);
3047+
GenTree* impSSE41Intrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);
3048+
GenTree* impSSE42Intrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);
3049+
GenTree* impAVXIntrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);
3050+
GenTree* impAVX2Intrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);
3051+
GenTree* impAESIntrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);
3052+
GenTree* impBMI1Intrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);
3053+
GenTree* impBMI2Intrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);
3054+
GenTree* impFMAIntrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);
3055+
GenTree* impLZCNTIntrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);
3056+
GenTree* impPCLMULQDQIntrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);
3057+
GenTree* impPOPCNTIntrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);
3058+
bool impTableDrivableHWIntrinsic(HWIntrinsicCategory category);
30993059
bool compSupportsHWIntrinsic(InstructionSet isa);
31003060
bool isScalarISA(InstructionSet isa);
3061+
int ivalOfHWIntrinsic(NamedIntrinsic intrinsic);
3062+
instruction instructionOfHWIntrinsicOnType(NamedIntrinsic intrinsic, var_types type);
3063+
HWIntrinsicCategory categoryOfHWIntrinsic(NamedIntrinsic intrinsic);
3064+
GenTreeArgList* buildArgList(int num);
31013065
#endif // _TARGET_XARCH_
31023066
#endif // FEATURE_HW_INTRINSICS
31033067
GenTreePtr impArrayAccessIntrinsic(CORINFO_CLASS_HANDLE clsHnd,

‎src/jit/compiler.hpp

+13
Original file line numberDiff line numberDiff line change
@@ -4891,6 +4891,19 @@ void GenTree::VisitOperands(TVisitor visitor)
48914891
return;
48924892
#endif // FEATURE_SIMD
48934893

4894+
#if FEATURE_HW_INTRINSICS
4895+
case GT_HWIntrinsic:
4896+
if ((this->AsHWIntrinsic()->gtOp1 != nullptr) && this->AsHWIntrinsic()->gtOp1->OperIsList())
4897+
{
4898+
this->AsHWIntrinsic()->gtOp1->VisitListOperands(visitor);
4899+
}
4900+
else
4901+
{
4902+
VisitBinOpOperands<TVisitor>(visitor);
4903+
}
4904+
return;
4905+
#endif // FEATURE_HW_INTRINSICS
4906+
48944907
// Special nodes
48954908
case GT_CMPXCHG:
48964909
{

‎src/jit/emit.h

+14
Original file line numberDiff line numberDiff line change
@@ -938,6 +938,7 @@ class emitter
938938
struct
939939
{
940940
regNumber _idReg3 : REGNUM_BITS;
941+
regNumber _idReg4 : REGNUM_BITS;
941942
};
942943
#endif // defined(_TARGET_XARCH_)
943944

@@ -1119,6 +1120,19 @@ class emitter
11191120
idAddr()->_idReg3 = reg;
11201121
assert(reg == idAddr()->_idReg3);
11211122
}
1123+
regNumber idReg4() const
1124+
{
1125+
assert(!idIsTiny());
1126+
assert(!idIsSmallDsc());
1127+
return idAddr()->_idReg4;
1128+
}
1129+
void idReg4(regNumber reg)
1130+
{
1131+
assert(!idIsTiny());
1132+
assert(!idIsSmallDsc());
1133+
idAddr()->_idReg4 = reg;
1134+
assert(reg == idAddr()->_idReg4);
1135+
}
11221136
#endif // defined(_TARGET_XARCH_)
11231137
#ifdef _TARGET_ARMARCH_
11241138
insOpts idInsOpt() const

‎src/jit/emitfmtsxarch.h

+2
Original file line numberDiff line numberDiff line change
@@ -110,6 +110,8 @@ IF_DEF(RRW_RRW_CNS, IS_R1_RW|IS_R2_RW, SCNS) // r/w reg , r/w r
110110

111111
IF_DEF(RWR_RRD_RRD, IS_R1_WR|IS_R2_RD|IS_R3_RD, NONE) // write reg , read reg2 , read reg3
112112
IF_DEF(RWR_RRD_RRD_CNS, IS_R1_WR|IS_R2_RD|IS_R3_RD, SCNS) // write reg , read reg2 , read reg3, const
113+
114+
IF_DEF(RWR_RRD_RRD_RRD, IS_R1_WR|IS_R2_RD|IS_R3_RD|IS_R4_RD, NONE) // write reg , read reg2 , read reg3 , read reg4
113115
//----------------------------------------------------------------------------
114116
// The following formats are used for direct addresses (e.g. static data members)
115117
//----------------------------------------------------------------------------

‎src/jit/emitxarch.cpp

+43-7
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,7 @@ bool emitter::IsDstDstSrcAVXInstruction(instruction ins)
9595
ins == INS_pmaxuw || ins == INS_pmaxud || ins == INS_vinserti128 || ins == INS_punpckhbw ||
9696
ins == INS_punpcklbw || ins == INS_punpckhqdq || ins == INS_punpcklqdq || ins == INS_punpckhwd ||
9797
ins == INS_punpcklwd || ins == INS_punpckhdq || ins == INS_packssdw || ins == INS_packsswb ||
98-
ins == INS_packuswb || ins == INS_packusdw || ins == INS_vperm2i128);
98+
ins == INS_packuswb || ins == INS_packusdw || ins == INS_vperm2i128 || ins == INS_pmuldq);
9999
}
100100

101101
// Returns true if the AVX instruction requires 3 operands that duplicate the source
@@ -3858,6 +3858,33 @@ void emitter::emitIns_R_R_R_I(
38583858
emitCurIGsize += sz;
38593859
}
38603860

3861+
void emitter::emitIns_R_R_R_R(
3862+
instruction ins, emitAttr attr, regNumber targetReg, regNumber reg1, regNumber reg2, regNumber reg3)
3863+
{
3864+
assert(ins == INS_vblendvps || ins == INS_vblendvpd || ins == INS_vpblendvb);
3865+
assert(UseVEXEncoding());
3866+
// Currently vex prefix only use three bytes mode.
3867+
// size = vex + opcode + ModR/M + 1-byte-cns(Reg) = 3 + 1 + 1 + 1 = 6
3868+
// TODO-XArch-CQ: We should create function which can calculate all kinds of AVX instructions size in future
3869+
UNATIVE_OFFSET sz = 6;
3870+
3871+
// AVX/AVX2 supports 4-reg format for vblendvps/vblendvpd/vpblendvb,
3872+
// which encodes the fourth register into imm8[7:4]
3873+
int ival = (reg3 - XMMBASE) << 4; // convert reg3 to ival
3874+
3875+
instrDesc* id = emitNewInstrCns(attr, ival);
3876+
id->idIns(ins);
3877+
id->idInsFmt(IF_RWR_RRD_RRD_RRD);
3878+
id->idReg1(targetReg);
3879+
id->idReg2(reg1);
3880+
id->idReg3(reg2);
3881+
id->idReg4(reg3);
3882+
3883+
id->idCodeSize(sz);
3884+
dispIns(id);
3885+
emitCurIGsize += sz;
3886+
}
3887+
38613888
/*****************************************************************************
38623889
*
38633890
* Add an instruction with a register + static member operands.
@@ -4797,19 +4824,19 @@ void emitter::emitIns_AX_R(instruction ins, emitAttr attr, regNumber ireg, regNu
47974824
}
47984825

47994826
#if FEATURE_HW_INTRINSICS
4800-
void emitter::emitIns_SIMD_R_R_R(instruction ins, regNumber reg, regNumber reg1, regNumber reg2, var_types simdtype)
4827+
void emitter::emitIns_SIMD_R_R_R(instruction ins, regNumber reg, regNumber reg1, regNumber reg2, emitAttr attr)
48014828
{
4802-
if (UseVEXEncoding() && reg1 != reg)
4829+
if (UseVEXEncoding())
48034830
{
4804-
emitIns_R_R_R(ins, emitTypeSize(simdtype), reg, reg1, reg2);
4831+
emitIns_R_R_R(ins, attr, reg, reg1, reg2);
48054832
}
48064833
else
48074834
{
48084835
if (reg1 != reg)
48094836
{
4810-
emitIns_R_R(INS_movaps, emitTypeSize(simdtype), reg, reg1);
4837+
emitIns_R_R(INS_movaps, attr, reg, reg1);
48114838
}
4812-
emitIns_R_R(ins, emitTypeSize(simdtype), reg, reg2);
4839+
emitIns_R_R(ins, attr, reg, reg2);
48134840
}
48144841
}
48154842
#endif
@@ -7048,6 +7075,14 @@ void emitter::emitDispIns(
70487075
val = emitGetInsSC(id);
70497076
goto PRINT_CONSTANT;
70507077
break;
7078+
case IF_RWR_RRD_RRD_RRD:
7079+
assert(IsAVXOnlyInstruction(ins));
7080+
assert(UseVEXEncoding());
7081+
printf("%s, ", emitRegName(id->idReg1(), attr));
7082+
printf("%s, ", emitRegName(id->idReg2(), attr));
7083+
printf("%s, ", emitRegName(id->idReg3(), attr));
7084+
printf("%s", emitRegName(id->idReg4(), attr));
7085+
break;
70517086
case IF_RRW_RRW_CNS:
70527087
printf("%s,", emitRegName(id->idReg1(), attr));
70537088
printf(" %s", emitRegName(id->idReg2(), attr));
@@ -9452,7 +9487,7 @@ BYTE* emitter::emitOutputRRR(BYTE* dst, instrDesc* id)
94529487

94539488
instruction ins = id->idIns();
94549489
assert(IsAVXInstruction(ins));
9455-
assert(IsThreeOperandAVXInstruction(ins));
9490+
assert(IsThreeOperandAVXInstruction(ins) || ins == INS_vblendvps || ins == INS_vblendvpd || ins == INS_vpblendvb);
94569491
regNumber targetReg = id->idReg1();
94579492
regNumber src1 = id->idReg2();
94589493
regNumber src2 = id->idReg3();
@@ -10718,6 +10753,7 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
1071810753
sz = emitSizeOfInsDsc(id);
1071910754
break;
1072010755
case IF_RWR_RRD_RRD_CNS:
10756+
case IF_RWR_RRD_RRD_RRD:
1072110757
dst = emitOutputRRR(dst, id);
1072210758
sz = emitSizeOfInsDsc(id);
1072310759
dst += emitOutputByte(dst, emitGetInsSC(id));

‎src/jit/emitxarch.h

+3-1
Original file line numberDiff line numberDiff line change
@@ -369,6 +369,8 @@ void emitIns_R_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg
369369

370370
void emitIns_R_R_R_I(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber reg3, int ival);
371371

372+
void emitIns_R_R_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber reg3, regNumber reg4);
373+
372374
void emitIns_S(instruction ins, emitAttr attr, int varx, int offs);
373375

374376
void emitIns_S_R(instruction ins, emitAttr attr, regNumber ireg, int varx, int offs);
@@ -424,7 +426,7 @@ void emitIns_R_AX(instruction ins, emitAttr attr, regNumber ireg, regNumber reg,
424426
void emitIns_AX_R(instruction ins, emitAttr attr, regNumber ireg, regNumber reg, unsigned mul, int disp);
425427

426428
#if FEATURE_HW_INTRINSICS
427-
void emitIns_SIMD_R_R_R(instruction ins, regNumber reg, regNumber reg1, regNumber reg2, var_types simdtype);
429+
void emitIns_SIMD_R_R_R(instruction ins, regNumber reg, regNumber reg1, regNumber reg2, emitAttr attr);
428430
#endif
429431

430432
#if FEATURE_STACK_FP_X87

‎src/jit/gentree.cpp

+52-7
Original file line numberDiff line numberDiff line change
@@ -327,6 +327,9 @@ void GenTree::InitNodeSize()
327327
GenTree::s_gtNodeSizes[GT_MOD] = TREE_NODE_SZ_LARGE;
328328
GenTree::s_gtNodeSizes[GT_UMOD] = TREE_NODE_SZ_LARGE;
329329
#endif
330+
#if FEATURE_HW_INTRINSICS
331+
GenTree::s_gtNodeSizes[GT_HWIntrinsic] = TREE_NODE_SZ_LARGE;
332+
#endif
330333
#ifdef FEATURE_PUT_STRUCT_ARG_STK
331334
// TODO-Throughput: This should not need to be a large node. The object info should be
332335
// obtained from the child node.
@@ -5671,6 +5674,16 @@ bool GenTree::TryGetUse(GenTree* def, GenTree*** use)
56715674
return TryGetUseBinOp(def, use);
56725675
#endif // FEATURE_SIMD
56735676

5677+
#ifdef FEATURE_HW_INTRINSICS
5678+
case GT_HWIntrinsic:
5679+
if ((this->AsHWIntrinsic()->gtOp1 != nullptr) && this->AsHWIntrinsic()->gtOp1->OperIsList())
5680+
{
5681+
return this->AsHWIntrinsic()->gtOp1->TryGetUseList(def, use);
5682+
}
5683+
5684+
return TryGetUseBinOp(def, use);
5685+
#endif // FEATURE_HW_INTRINSICS
5686+
56745687
// Special nodes
56755688
case GT_CMPXCHG:
56765689
{
@@ -7912,7 +7925,8 @@ GenTreePtr Compiler::gtCloneExpr(
79127925
copy = new (this, GT_HWIntrinsic)
79137926
GenTreeHWIntrinsic(hwintrinsicOp->TypeGet(), hwintrinsicOp->gtGetOp1(),
79147927
hwintrinsicOp->gtGetOp2IfPresent(), hwintrinsicOp->gtHWIntrinsicId,
7915-
hwintrinsicOp->gtSIMDBaseType, hwintrinsicOp->gtSIMDSize);
7928+
hwintrinsicOp->gtSIMDBaseType, hwintrinsicOp->gtSIMDSize,
7929+
hwintrinsicOp->gtNumArgs, hwintrinsicOp->gtIval);
79167930
}
79177931
break;
79187932
#endif
@@ -9211,6 +9225,24 @@ GenTreeUseEdgeIterator::GenTreeUseEdgeIterator(GenTree* node)
92119225
return;
92129226
#endif // FEATURE_SIMD
92139227

9228+
#if FEATURE_HW_INTRINSICS
9229+
case GT_HWIntrinsic:
9230+
if (m_node->AsHWIntrinsic()->gtOp1 == nullptr)
9231+
{
9232+
assert(m_node->NullOp1Legal());
9233+
m_state = -1;
9234+
}
9235+
else if (m_node->AsHWIntrinsic()->gtOp1->OperIsList())
9236+
{
9237+
SetEntryStateForList(m_node->AsHWIntrinsic()->gtOp1);
9238+
}
9239+
else
9240+
{
9241+
SetEntryStateForBinOp();
9242+
}
9243+
return;
9244+
#endif // FEATURE_HW_INTRINSICS
9245+
92149246
// LEA, which may have no first operand
92159247
case GT_LEA:
92169248
if (m_node->AsAddrMode()->gtOp1 == nullptr)
@@ -17864,28 +17896,41 @@ bool GenTree::isCommutativeSIMDIntrinsic()
1786417896

1786517897
#if FEATURE_HW_INTRINSICS
1786617898
GenTreeHWIntrinsic* Compiler::gtNewSimdHWIntrinsicNode(
17867-
var_types type, GenTree* op1, NamedIntrinsic hwIntrinsicID, var_types baseType, unsigned size)
17899+
var_types type, GenTree* op1, NamedIntrinsic hwIntrinsicID, var_types baseType, unsigned simdSize)
1786817900
{
17869-
return new (this, GT_HWIntrinsic) GenTreeHWIntrinsic(type, op1, hwIntrinsicID, baseType, size);
17901+
int numArgs = 0;
17902+
17903+
if (op1 != nullptr && op1->OperIsList())
17904+
{
17905+
for (GenTreeArgList* list = op1->AsArgList(); list != nullptr; list = list->Rest())
17906+
{
17907+
numArgs++;
17908+
}
17909+
}
17910+
else if (op1 != nullptr)
17911+
{
17912+
numArgs = 1;
17913+
}
17914+
return new (this, GT_HWIntrinsic) GenTreeHWIntrinsic(type, op1, hwIntrinsicID, baseType, simdSize, numArgs, -1);
1787017915
}
1787117916

1787217917
GenTreeHWIntrinsic* Compiler::gtNewSimdHWIntrinsicNode(
17873-
var_types type, GenTree* op1, GenTree* op2, NamedIntrinsic hwIntrinsicID, var_types baseType, unsigned size)
17918+
var_types type, GenTree* op1, GenTree* op2, NamedIntrinsic hwIntrinsicID, var_types baseType, unsigned simdSize)
1787417919
{
17875-
return new (this, GT_HWIntrinsic) GenTreeHWIntrinsic(type, op1, op2, hwIntrinsicID, baseType, size);
17920+
return new (this, GT_HWIntrinsic) GenTreeHWIntrinsic(type, op1, op2, hwIntrinsicID, baseType, simdSize, 2, -1);
1787617921
}
1787717922

1787817923
GenTreeHWIntrinsic* Compiler::gtNewScalarHWIntrinsicNode(var_types type, GenTree* op1, NamedIntrinsic hwIntrinsicID)
1787917924
{
17880-
return new (this, GT_HWIntrinsic) GenTreeHWIntrinsic(type, op1, hwIntrinsicID, TYP_UNKNOWN, 0);
17925+
return new (this, GT_HWIntrinsic) GenTreeHWIntrinsic(type, op1, hwIntrinsicID, TYP_UNKNOWN, 0, 1, -1);
1788117926
}
1788217927

1788317928
GenTreeHWIntrinsic* Compiler::gtNewScalarHWIntrinsicNode(var_types type,
1788417929
GenTree* op1,
1788517930
GenTree* op2,
1788617931
NamedIntrinsic hwIntrinsicID)
1788717932
{
17888-
return new (this, GT_HWIntrinsic) GenTreeHWIntrinsic(type, op1, op2, hwIntrinsicID, TYP_UNKNOWN, 0);
17933+
return new (this, GT_HWIntrinsic) GenTreeHWIntrinsic(type, op1, op2, hwIntrinsicID, TYP_UNKNOWN, 0, 2, -1);
1788917934
}
1789017935

1789117936
//---------------------------------------------------------------------------------------

0 commit comments

Comments
 (0)