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Commit fb08741

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FeiPengIntelFeiPengIntel
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Add emitIns_AR_R_I for vextracti/f128
1 parent a9cebd5 commit fb08741

5 files changed

+109
-3
lines changed

‎src/jit/emitfmtsxarch.h

+4
Original file line numberDiff line numberDiff line change
@@ -139,6 +139,8 @@ IF_DEF(MRD_CNS, IS_GM_RD, DSP_CNS) // read [mem], const
139139
IF_DEF(MWR_CNS, IS_GM_WR, DSP_CNS) // write [mem], const
140140
IF_DEF(MRW_CNS, IS_GM_RW, DSP_CNS) // r/w [mem], const
141141

142+
IF_DEF(MWR_RRD_CNS, IS_GM_WR|IS_R1_RD, DSP_CNS) // write [mem], read reg, const
143+
142144
IF_DEF(MRW_SHF, IS_GM_RW, DSP_CNS) // shift [mem], const
143145

144146
//----------------------------------------------------------------------------
@@ -194,6 +196,8 @@ IF_DEF(ARD_CNS, IS_AM_RD, AMD_CNS) // read [adr], const
194196
IF_DEF(AWR_CNS, IS_AM_WR, AMD_CNS) // write [adr], const
195197
IF_DEF(ARW_CNS, IS_AM_RW, AMD_CNS) // r/w [adr], const
196198

199+
IF_DEF(AWR_RRD_CNS, IS_AM_WR|IS_R1_RD, AMD_CNS) // write [adr], read reg, const
200+
197201
IF_DEF(ARW_SHF, IS_AM_RW, AMD_CNS) // shift [adr], const
198202

199203

‎src/jit/emitxarch.cpp

+101
Original file line numberDiff line numberDiff line change
@@ -2730,6 +2730,9 @@ emitter::insFormat emitter::emitMapFmtAtoM(insFormat fmt)
27302730
case IF_ARW_CNS:
27312731
return IF_MRW_CNS;
27322732

2733+
case IF_AWR_RRD_CNS:
2734+
return IF_MWR_RRD_CNS;
2735+
27332736
case IF_ARW_SHF:
27342737
return IF_MRW_SHF;
27352738

@@ -5067,6 +5070,32 @@ void emitter::emitIns_AR_R(instruction ins, emitAttr attr, regNumber ireg, regNu
50675070
emitAdjustStackDepthPushPop(ins);
50685071
}
50695072

5073+
#ifndef LEGACY_BACKEND
5074+
void emitter::emitIns_AR_R_I(instruction ins, emitAttr attr, regNumber base, int disp, regNumber ireg, int ival)
5075+
{
5076+
assert(ins == INS_vextracti128 || ins == INS_vextractf128);
5077+
assert(base != REG_NA);
5078+
assert(ireg != REG_NA);
5079+
UNATIVE_OFFSET sz;
5080+
instrDesc* id = emitNewInstrAmdCns(attr, disp, ival);
5081+
5082+
id->idIns(ins);
5083+
id->idInsFmt(IF_AWR_RRD_CNS);
5084+
id->idAddr()->iiaAddrMode.amBaseReg = base;
5085+
id->idAddr()->iiaAddrMode.amIndxReg = REG_NA;
5086+
id->idReg1(ireg);
5087+
5088+
assert(emitGetInsAmdAny(id) == disp); // make sure "disp" is stored properly
5089+
5090+
// the code size of "vextracti/f128 [mem], ymm, imm8" is 6 byte
5091+
sz = 6;
5092+
id->idCodeSize(sz);
5093+
5094+
dispIns(id);
5095+
emitCurIGsize += sz;
5096+
}
5097+
#endif
5098+
50705099
void emitter::emitIns_AI_R(instruction ins, emitAttr attr, regNumber ireg, ssize_t disp)
50715100
{
50725101
UNATIVE_OFFSET sz;
@@ -7790,6 +7819,32 @@ void emitter::emitDispIns(
77907819
break;
77917820
}
77927821

7822+
case IF_AWR_RRD_CNS:
7823+
{
7824+
assert(ins == INS_vextracti128 || ins == INS_vextractf128);
7825+
// vextracti/f128 extracts 128-bit data, so we fix sstr as "xmm ptr"
7826+
sstr = codeGen->genSizeStr(EA_ATTR(16));
7827+
printf(sstr);
7828+
emitDispAddrMode(id);
7829+
printf(", %s", emitRegName(id->idReg1(), attr));
7830+
7831+
emitGetInsAmdCns(id, &cnsVal);
7832+
7833+
val = cnsVal.cnsVal;
7834+
printf(", ");
7835+
7836+
if (cnsVal.cnsReloc)
7837+
{
7838+
emitDispReloc(val);
7839+
}
7840+
else
7841+
{
7842+
goto PRINT_CONSTANT;
7843+
}
7844+
7845+
break;
7846+
}
7847+
77937848
case IF_RWR_RRD_ARD:
77947849
printf("%s, %s, %s", emitRegName(id->idReg1(), attr), emitRegName(id->idReg2(), attr), sstr);
77957850
emitDispAddrMode(id);
@@ -8166,6 +8221,32 @@ void emitter::emitDispIns(
81668221
break;
81678222
}
81688223

8224+
case IF_MWR_RRD_CNS:
8225+
{
8226+
assert(ins == INS_vextracti128 || ins == INS_vextractf128);
8227+
// vextracti/f128 extracts 128-bit data, so we fix sstr as "xmm ptr"
8228+
sstr = codeGen->genSizeStr(EA_ATTR(16));
8229+
printf(sstr);
8230+
offs = emitGetInsDsp(id);
8231+
emitDispClsVar(id->idAddr()->iiaFieldHnd, offs, ID_INFO_DSP_RELOC);
8232+
printf(", %s", emitRegName(id->idReg1(), attr));
8233+
emitGetInsDcmCns(id, &cnsVal);
8234+
8235+
val = cnsVal.cnsVal;
8236+
printf(", ");
8237+
8238+
if (cnsVal.cnsReloc)
8239+
{
8240+
emitDispReloc(val);
8241+
}
8242+
else
8243+
{
8244+
goto PRINT_CONSTANT;
8245+
}
8246+
8247+
break;
8248+
}
8249+
81698250
case IF_RWR_RRD_MRD:
81708251
printf("%s, %s, %s", emitRegName(id->idReg1(), attr), emitRegName(id->idReg2(), attr), sstr);
81718252
offs = emitGetInsDsp(id);
@@ -12218,6 +12299,15 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
1221812299
sz = emitSizeOfInsDsc(id);
1221912300
break;
1222012301

12302+
case IF_AWR_RRD_CNS:
12303+
assert(ins == INS_vextracti128 || ins == INS_vextractf128);
12304+
assert(UseVEXEncoding());
12305+
emitGetInsAmdCns(id, &cnsVal);
12306+
code = insCodeMR(ins);
12307+
dst = emitOutputAM(dst, id, code, &cnsVal);
12308+
sz = emitSizeOfInsDsc(id);
12309+
break;
12310+
1222112311
case IF_RRD_ARD:
1222212312
case IF_RWR_ARD:
1222312313
case IF_RRW_ARD:
@@ -12530,6 +12620,17 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
1253012620
sz = emitSizeOfInsDsc(id);
1253112621
break;
1253212622

12623+
case IF_MWR_RRD_CNS:
12624+
assert(ins == INS_vextracti128 || ins == INS_vextractf128);
12625+
assert(UseVEXEncoding());
12626+
emitGetInsDcmCns(id, &cnsVal);
12627+
code = insCodeMR(ins);
12628+
// only AVX2 vextracti128 and AVX vextractf128 can reach this path,
12629+
// they do not need VEX.vvvv to encode the register operand
12630+
dst = emitOutputCV(dst, id, code, &cnsVal);
12631+
sz = emitSizeOfInsDsc(id);
12632+
break;
12633+
1253312634
case IF_RRD_MRD:
1253412635
case IF_RWR_MRD:
1253512636
case IF_RRW_MRD:

‎src/jit/emitxarch.h

+1
Original file line numberDiff line numberDiff line change
@@ -416,6 +416,7 @@ void emitIns_R_R_A_I(
416416
instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, GenTreeIndir* indir, int ival, insFormat fmt);
417417
void emitIns_R_R_AR_I(
418418
instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber base, int offs, int ival);
419+
void emitIns_AR_R_I(instruction ins, emitAttr attr, regNumber base, int disp, regNumber ireg, int ival);
419420
#endif // !LEGACY_BACKEND
420421

421422
void emitIns_R_R_C_I(

‎src/jit/hwintrinsiccodegenxarch.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -1473,7 +1473,7 @@ void CodeGen::genAvxOrAvx2Intrinsic(GenTreeHWIntrinsic* node)
14731473
{
14741474
if (intrinsicID == NI_AVX_ExtractVector128 || intrinsicID == NI_AVX2_ExtractVector128)
14751475
{
1476-
emit->emitIns_R_AR_I(ins, attr, op2Reg, op1Reg, 0, (int)i);
1476+
emit->emitIns_AR_R_I(ins, attr, op1Reg, 0, op2Reg, (int)i);
14771477
}
14781478
else if (op2->TypeGet() == TYP_I_IMPL)
14791479
{

‎src/jit/instrsxarch.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -474,8 +474,8 @@ INST3( vpbroadcastb, "pbroadcastb" , 0, IUM_WR, 0, 0, BAD_CODE, BAD_CODE, SS
474474
INST3( vpbroadcastw, "pbroadcastw" , 0, IUM_WR, 0, 0, BAD_CODE, BAD_CODE, SSE38(0x79)) // Broadcast int16 value from reg/memory to entire ymm register
475475
INST3( vpbroadcastd, "pbroadcastd" , 0, IUM_WR, 0, 0, BAD_CODE, BAD_CODE, SSE38(0x58)) // Broadcast int32 value from reg/memory to entire ymm register
476476
INST3( vpbroadcastq, "pbroadcastq" , 0, IUM_WR, 0, 0, BAD_CODE, BAD_CODE, SSE38(0x59)) // Broadcast int64 value from reg/memory to entire ymm register
477-
INST3( vextractf128, "extractf128" , 0, IUM_WR, 0, 0, SSE3A(0x19), BAD_CODE, SSE3A(0x19)) // Extract 128-bit packed floating point values
478-
INST3( vextracti128, "extracti128" , 0, IUM_WR, 0, 0, SSE3A(0x39), BAD_CODE, SSE3A(0x39)) // Extract 128-bit packed integer values
477+
INST3( vextractf128, "extractf128" , 0, IUM_WR, 0, 0, SSE3A(0x19), BAD_CODE, BAD_CODE) // Extract 128-bit packed floating point values
478+
INST3( vextracti128, "extracti128" , 0, IUM_WR, 0, 0, SSE3A(0x39), BAD_CODE, BAD_CODE) // Extract 128-bit packed integer values
479479
INST3( vinsertf128, "insertf128" , 0, IUM_WR, 0, 0, BAD_CODE, BAD_CODE, SSE3A(0x18)) // Insert 128-bit packed floating point values
480480
INST3( vinserti128, "inserti128" , 0, IUM_WR, 0, 0, BAD_CODE, BAD_CODE, SSE3A(0x38)) // Insert 128-bit packed integer values
481481
INST3( vzeroupper, "zeroupper" , 0, IUM_WR, 0, 0, 0xC577F8, BAD_CODE, BAD_CODE) // Zero upper 128-bits of all YMM regs (includes 2-byte fixed VEX prefix)

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