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lowerarmarch.cpp
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lowerarmarch.cpp
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// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
/*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XX XX
XX Lowering for ARM and ARM64 common code XX
XX XX
XX This encapsulates common logic for lowering trees for the ARM and ARM64 XX
XX architectures. For a more detailed view of what is lowering, please XX
XX take a look at Lower.cpp XX
XX XX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
*/
#include "jitpch.h"
#ifdef _MSC_VER
#pragma hdrstop
#endif
#ifdef TARGET_ARMARCH // This file is ONLY used for ARM and ARM64 architectures
#include "jit.h"
#include "sideeffects.h"
#include "lower.h"
#include "lsra.h"
#ifdef FEATURE_HW_INTRINSICS
#include "hwintrinsic.h"
#endif
//------------------------------------------------------------------------
// IsCallTargetInRange: Can a call target address be encoded in-place?
//
// Return Value:
// True if the addr fits into the range.
//
bool Lowering::IsCallTargetInRange(void* addr)
{
return comp->codeGen->validImmForBL((ssize_t)addr);
}
//------------------------------------------------------------------------
// IsContainableImmed: Is an immediate encodable in-place?
//
// Return Value:
// True if the immediate can be folded into an instruction,
// for example small enough and non-relocatable.
//
bool Lowering::IsContainableImmed(GenTree* parentNode, GenTree* childNode) const
{
if (!varTypeIsFloating(parentNode->TypeGet()))
{
#ifdef TARGET_ARM64
if (parentNode->OperIsRelop() && childNode->IsFPZero())
{
// Contain 0.0 constant in fcmp on arm64
// TODO: Enable for arm too (vcmp)
// We currently don't emit these for floating points
assert(!parentNode->OperIs(GT_TEST_EQ, GT_TEST_NE));
return true;
}
#endif
// Make sure we have an actual immediate
if (!childNode->IsCnsIntOrI())
return false;
if (childNode->AsIntCon()->ImmedValNeedsReloc(comp))
return false;
// TODO-CrossBitness: we wouldn't need the cast below if GenTreeIntCon::gtIconVal had target_ssize_t type.
target_ssize_t immVal = (target_ssize_t)childNode->AsIntCon()->gtIconVal;
emitAttr attr = emitActualTypeSize(childNode->TypeGet());
emitAttr size = EA_SIZE(attr);
#ifdef TARGET_ARM
insFlags flags = parentNode->gtSetFlags() ? INS_FLAGS_SET : INS_FLAGS_DONT_CARE;
#endif
switch (parentNode->OperGet())
{
case GT_ADD:
case GT_SUB:
#ifdef TARGET_ARM64
return emitter::emitIns_valid_imm_for_add(immVal, size);
case GT_CMPXCHG:
case GT_LOCKADD:
case GT_XORR:
case GT_XAND:
case GT_XADD:
return comp->compOpportunisticallyDependsOn(InstructionSet_Atomics)
? false
: emitter::emitIns_valid_imm_for_add(immVal, size);
#elif defined(TARGET_ARM)
return emitter::emitIns_valid_imm_for_add(immVal, flags);
#endif
break;
#ifdef TARGET_ARM64
case GT_EQ:
case GT_NE:
case GT_LT:
case GT_LE:
case GT_GE:
case GT_GT:
case GT_BOUNDS_CHECK:
return emitter::emitIns_valid_imm_for_cmp(immVal, size);
case GT_AND:
case GT_OR:
case GT_XOR:
case GT_TEST_EQ:
case GT_TEST_NE:
return emitter::emitIns_valid_imm_for_alu(immVal, size);
case GT_JCMP:
assert(((parentNode->gtFlags & GTF_JCMP_TST) == 0) ? (immVal == 0) : isPow2(immVal));
return true;
#elif defined(TARGET_ARM)
case GT_EQ:
case GT_NE:
case GT_LT:
case GT_LE:
case GT_GE:
case GT_GT:
case GT_CMP:
case GT_AND:
case GT_OR:
case GT_XOR:
return emitter::emitIns_valid_imm_for_alu(immVal);
#endif // TARGET_ARM
#ifdef TARGET_ARM64
case GT_STORE_LCL_FLD:
case GT_STORE_LCL_VAR:
if (immVal == 0)
return true;
break;
#endif
default:
break;
}
}
return false;
}
//------------------------------------------------------------------------
// LowerStoreLoc: Lower a store of a lclVar
//
// Arguments:
// storeLoc - the local store (GT_STORE_LCL_FLD or GT_STORE_LCL_VAR)
//
// Notes:
// This involves:
// - Widening operations of unsigneds.
//
void Lowering::LowerStoreLoc(GenTreeLclVarCommon* storeLoc)
{
GenTree* op1 = storeLoc->gtGetOp1();
if ((storeLoc->gtOper == GT_STORE_LCL_VAR) && (op1->gtOper == GT_CNS_INT))
{
// Try to widen the ops if they are going into a local var.
GenTreeIntCon* con = op1->AsIntCon();
ssize_t ival = con->gtIconVal;
unsigned varNum = storeLoc->GetLclNum();
LclVarDsc* varDsc = comp->lvaGetDesc(varNum);
if (varDsc->lvIsSIMDType())
{
noway_assert(storeLoc->gtType != TYP_STRUCT);
}
unsigned size = genTypeSize(storeLoc);
// If we are storing a constant into a local variable
// we extend the size of the store here
if ((size < 4) && !varTypeIsStruct(varDsc))
{
if (!varTypeIsUnsigned(varDsc))
{
if (genTypeSize(storeLoc) == 1)
{
if ((ival & 0x7f) != ival)
{
ival = ival | 0xffffff00;
}
}
else
{
assert(genTypeSize(storeLoc) == 2);
if ((ival & 0x7fff) != ival)
{
ival = ival | 0xffff0000;
}
}
}
// A local stack slot is at least 4 bytes in size, regardless of
// what the local var is typed as, so auto-promote it here
// unless it is a field of a promoted struct
// TODO-CQ: if the field is promoted shouldn't we also be able to do this?
if (!varDsc->lvIsStructField)
{
storeLoc->gtType = TYP_INT;
con->SetIconValue(ival);
}
}
}
if (storeLoc->OperIs(GT_STORE_LCL_FLD))
{
// We should only encounter this for lclVars that are lvDoNotEnregister.
verifyLclFldDoNotEnregister(storeLoc->GetLclNum());
}
ContainCheckStoreLoc(storeLoc);
}
//------------------------------------------------------------------------
// LowerStoreIndir: Determine addressing mode for an indirection, and whether operands are contained.
//
// Arguments:
// node - The indirect store node (GT_STORE_IND) of interest
//
// Return Value:
// None.
//
void Lowering::LowerStoreIndir(GenTreeStoreInd* node)
{
ContainCheckStoreIndir(node);
}
//------------------------------------------------------------------------
// LowerMul: Lower a GT_MUL/GT_MULHI/GT_MUL_LONG node.
//
// For ARM64 recognized GT_MULs that can be turned into GT_MUL_LONGs, as
// those are cheaper. Performs contaiment checks.
//
// Arguments:
// mul - The node to lower
//
// Return Value:
// The next node to lower.
//
GenTree* Lowering::LowerMul(GenTreeOp* mul)
{
assert(mul->OperIsMul());
#ifdef TARGET_ARM64
if (comp->opts.OptimizationEnabled() && mul->OperIs(GT_MUL) && mul->IsValidLongMul())
{
GenTreeCast* op1 = mul->gtGetOp1()->AsCast();
GenTree* op2 = mul->gtGetOp2();
mul->ClearOverflow();
mul->ClearUnsigned();
if (op1->IsUnsigned())
{
mul->SetUnsigned();
}
mul->gtOp1 = op1->CastOp();
BlockRange().Remove(op1);
if (op2->OperIs(GT_CAST))
{
mul->gtOp2 = op2->AsCast()->CastOp();
BlockRange().Remove(op2);
}
else
{
assert(op2->IsIntegralConst());
assert(FitsIn<int32_t>(op2->AsIntConCommon()->IntegralValue()));
op2->ChangeType(TYP_INT);
}
mul->ChangeOper(GT_MUL_LONG);
}
#endif // TARGET_ARM64
ContainCheckMul(mul);
return mul->gtNext;
}
//------------------------------------------------------------------------
// LowerBlockStore: Lower a block store node
//
// Arguments:
// blkNode - The block store node to lower
//
void Lowering::LowerBlockStore(GenTreeBlk* blkNode)
{
GenTree* dstAddr = blkNode->Addr();
GenTree* src = blkNode->Data();
unsigned size = blkNode->Size();
if (blkNode->OperIsInitBlkOp())
{
if (src->OperIs(GT_INIT_VAL))
{
src->SetContained();
src = src->AsUnOp()->gtGetOp1();
}
if (blkNode->OperIs(GT_STORE_OBJ))
{
blkNode->SetOper(GT_STORE_BLK);
}
if (!blkNode->OperIs(GT_STORE_DYN_BLK) && (size <= INITBLK_UNROLL_LIMIT) && src->OperIs(GT_CNS_INT))
{
blkNode->gtBlkOpKind = GenTreeBlk::BlkOpKindUnroll;
// The fill value of an initblk is interpreted to hold a
// value of (unsigned int8) however a constant of any size
// may practically reside on the evaluation stack. So extract
// the lower byte out of the initVal constant and replicate
// it to a larger constant whose size is sufficient to support
// the largest width store of the desired inline expansion.
ssize_t fill = src->AsIntCon()->IconValue() & 0xFF;
if (fill == 0)
{
#ifdef TARGET_ARM64
// On ARM64 we can just use REG_ZR instead of having to load
// the constant into a real register like on ARM32.
src->SetContained();
#endif
}
#ifdef TARGET_ARM64
else if (size >= REGSIZE_BYTES)
{
fill *= 0x0101010101010101LL;
src->gtType = TYP_LONG;
}
#endif
else
{
fill *= 0x01010101;
}
src->AsIntCon()->SetIconValue(fill);
ContainBlockStoreAddress(blkNode, size, dstAddr);
}
else
{
blkNode->gtBlkOpKind = GenTreeBlk::BlkOpKindHelper;
}
}
else
{
assert(src->OperIs(GT_IND, GT_LCL_VAR, GT_LCL_FLD));
src->SetContained();
if (src->OperIs(GT_IND))
{
// TODO-Cleanup: Make sure that GT_IND lowering didn't mark the source address as contained.
// Sometimes the GT_IND type is a non-struct type and then GT_IND lowering may contain the
// address, not knowing that GT_IND is part of a block op that has containment restrictions.
src->AsIndir()->Addr()->ClearContained();
}
else if (src->OperIs(GT_LCL_VAR))
{
// TODO-1stClassStructs: for now we can't work with STORE_BLOCK source in register.
const unsigned srcLclNum = src->AsLclVar()->GetLclNum();
comp->lvaSetVarDoNotEnregister(srcLclNum DEBUGARG(DoNotEnregisterReason::BlockOp));
}
if (blkNode->OperIs(GT_STORE_OBJ))
{
if (!blkNode->AsObj()->GetLayout()->HasGCPtr())
{
blkNode->SetOper(GT_STORE_BLK);
}
else if (dstAddr->OperIsLocalAddr() && (size <= CPBLK_UNROLL_LIMIT))
{
// If the size is small enough to unroll then we need to mark the block as non-interruptible
// to actually allow unrolling. The generated code does not report GC references loaded in the
// temporary register(s) used for copying.
blkNode->SetOper(GT_STORE_BLK);
blkNode->gtBlkOpGcUnsafe = true;
}
}
if (blkNode->OperIs(GT_STORE_OBJ))
{
assert((dstAddr->TypeGet() == TYP_BYREF) || (dstAddr->TypeGet() == TYP_I_IMPL));
blkNode->gtBlkOpKind = GenTreeBlk::BlkOpKindUnroll;
}
else if (blkNode->OperIs(GT_STORE_BLK) && (size <= CPBLK_UNROLL_LIMIT))
{
blkNode->gtBlkOpKind = GenTreeBlk::BlkOpKindUnroll;
if (src->OperIs(GT_IND))
{
ContainBlockStoreAddress(blkNode, size, src->AsIndir()->Addr());
}
ContainBlockStoreAddress(blkNode, size, dstAddr);
}
else
{
assert(blkNode->OperIs(GT_STORE_BLK, GT_STORE_DYN_BLK));
blkNode->gtBlkOpKind = GenTreeBlk::BlkOpKindHelper;
}
}
}
//------------------------------------------------------------------------
// ContainBlockStoreAddress: Attempt to contain an address used by an unrolled block store.
//
// Arguments:
// blkNode - the block store node
// size - the block size
// addr - the address node to try to contain
//
void Lowering::ContainBlockStoreAddress(GenTreeBlk* blkNode, unsigned size, GenTree* addr)
{
assert(blkNode->OperIs(GT_STORE_BLK) && (blkNode->gtBlkOpKind == GenTreeBlk::BlkOpKindUnroll));
assert(size < INT32_MAX);
if (addr->OperIsLocalAddr())
{
addr->SetContained();
return;
}
if (!addr->OperIs(GT_ADD) || addr->gtOverflow() || !addr->AsOp()->gtGetOp2()->OperIs(GT_CNS_INT))
{
return;
}
GenTreeIntCon* offsetNode = addr->AsOp()->gtGetOp2()->AsIntCon();
ssize_t offset = offsetNode->IconValue();
#ifdef TARGET_ARM
// All integer load/store instructions on Arm support offsets in range -255..255.
// Of course, this is a rather conservative check.
if ((offset < -255) || (offset > 255) || (offset + static_cast<int>(size) > 256))
{
return;
}
#endif // TARGET_ARM
if (!IsSafeToContainMem(blkNode, addr))
{
return;
}
BlockRange().Remove(offsetNode);
addr->ChangeOper(GT_LEA);
addr->AsAddrMode()->SetIndex(nullptr);
addr->AsAddrMode()->SetScale(0);
addr->AsAddrMode()->SetOffset(static_cast<int>(offset));
addr->SetContained();
}
//------------------------------------------------------------------------
// LowerCast: Lower GT_CAST(srcType, DstType) nodes.
//
// Arguments:
// tree - GT_CAST node to be lowered
//
// Return Value:
// None.
//
// Notes:
// Casts from float/double to a smaller int type are transformed as follows:
// GT_CAST(float/double, byte) = GT_CAST(GT_CAST(float/double, int32), byte)
// GT_CAST(float/double, sbyte) = GT_CAST(GT_CAST(float/double, int32), sbyte)
// GT_CAST(float/double, int16) = GT_CAST(GT_CAST(double/double, int32), int16)
// GT_CAST(float/double, uint16) = GT_CAST(GT_CAST(double/double, int32), uint16)
//
// Note that for the overflow conversions we still depend on helper calls and
// don't expect to see them here.
// i) GT_CAST(float/double, int type with overflow detection)
//
void Lowering::LowerCast(GenTree* tree)
{
assert(tree->OperGet() == GT_CAST);
JITDUMP("LowerCast for: ");
DISPNODE(tree);
JITDUMP("\n");
GenTree* op1 = tree->AsOp()->gtOp1;
var_types dstType = tree->CastToType();
var_types srcType = genActualType(op1->TypeGet());
var_types tmpType = TYP_UNDEF;
if (varTypeIsFloating(srcType))
{
noway_assert(!tree->gtOverflow());
assert(!varTypeIsSmall(dstType)); // fgMorphCast creates intermediate casts when converting from float to small
// int.
}
assert(!varTypeIsSmall(srcType));
if (tmpType != TYP_UNDEF)
{
GenTree* tmp = comp->gtNewCastNode(tmpType, op1, tree->IsUnsigned(), tmpType);
tmp->gtFlags |= (tree->gtFlags & (GTF_OVERFLOW | GTF_EXCEPT));
tree->gtFlags &= ~GTF_UNSIGNED;
tree->AsOp()->gtOp1 = tmp;
BlockRange().InsertAfter(op1, tmp);
}
// Now determine if we have operands that should be contained.
ContainCheckCast(tree->AsCast());
}
//------------------------------------------------------------------------
// LowerRotate: Lower GT_ROL and GT_ROR nodes.
//
// Arguments:
// tree - the node to lower
//
// Return Value:
// None.
//
void Lowering::LowerRotate(GenTree* tree)
{
if (tree->OperGet() == GT_ROL)
{
// There is no ROL instruction on ARM. Convert ROL into ROR.
GenTree* rotatedValue = tree->AsOp()->gtOp1;
unsigned rotatedValueBitSize = genTypeSize(rotatedValue->gtType) * 8;
GenTree* rotateLeftIndexNode = tree->AsOp()->gtOp2;
if (rotateLeftIndexNode->IsCnsIntOrI())
{
ssize_t rotateLeftIndex = rotateLeftIndexNode->AsIntCon()->gtIconVal;
ssize_t rotateRightIndex = rotatedValueBitSize - rotateLeftIndex;
rotateLeftIndexNode->AsIntCon()->gtIconVal = rotateRightIndex;
}
else
{
GenTree* tmp = comp->gtNewOperNode(GT_NEG, genActualType(rotateLeftIndexNode->gtType), rotateLeftIndexNode);
BlockRange().InsertAfter(rotateLeftIndexNode, tmp);
tree->AsOp()->gtOp2 = tmp;
}
tree->ChangeOper(GT_ROR);
}
ContainCheckShiftRotate(tree->AsOp());
}
#ifdef FEATURE_SIMD
//----------------------------------------------------------------------------------------------
// Lowering::LowerSIMD: Perform containment analysis for a SIMD intrinsic node.
//
// Arguments:
// simdNode - The SIMD intrinsic node.
//
void Lowering::LowerSIMD(GenTreeSIMD* simdNode)
{
assert(simdNode->gtType != TYP_SIMD32);
if (simdNode->TypeGet() == TYP_SIMD12)
{
// GT_SIMD node requiring to produce TYP_SIMD12 in fact
// produces a TYP_SIMD16 result
simdNode->gtType = TYP_SIMD16;
}
ContainCheckSIMD(simdNode);
}
#endif // FEATURE_SIMD
#ifdef FEATURE_HW_INTRINSICS
//----------------------------------------------------------------------------------------------
// LowerHWIntrinsicFusedMultiplyAddScalar: Lowers AdvSimd_FusedMultiplyAddScalar intrinsics
// when some of the operands are negated by "containing" such negation.
//
// Arguments:
// node - The original hardware intrinsic node
//
// | op1 | op2 | op3 |
// | + | + | + | AdvSimd_FusedMultiplyAddScalar
// | + | + | - | AdvSimd_FusedMultiplySubtractScalar
// | + | - | + | AdvSimd_FusedMultiplySubtractScalar
// | + | - | - | AdvSimd_FusedMultiplyAddScalar
// | - | + | + | AdvSimd_FusedMultiplySubtractNegatedScalar
// | - | + | - | AdvSimd_FusedMultiplyAddNegatedScalar
// | - | - | + | AdvSimd_FusedMultiplyAddNegatedScalar
// | - | - | - | AdvSimd_FusedMultiplySubtractNegatedScalar
//
void Lowering::LowerHWIntrinsicFusedMultiplyAddScalar(GenTreeHWIntrinsic* node)
{
assert(node->GetHWIntrinsicId() == NI_AdvSimd_FusedMultiplyAddScalar);
GenTree* op1 = node->Op(1);
GenTree* op2 = node->Op(2);
GenTree* op3 = node->Op(3);
auto lowerOperand = [this](GenTree* op) {
bool wasNegated = false;
if (op->OperIsHWIntrinsic() &&
((op->AsHWIntrinsic()->GetHWIntrinsicId() == NI_AdvSimd_Arm64_DuplicateToVector64) ||
(op->AsHWIntrinsic()->GetHWIntrinsicId() == NI_Vector64_CreateScalarUnsafe)))
{
GenTreeHWIntrinsic* createVector64 = op->AsHWIntrinsic();
GenTree* valueOp = createVector64->Op(1);
if (valueOp->OperIs(GT_NEG))
{
createVector64->Op(1) = valueOp->gtGetOp1();
BlockRange().Remove(valueOp);
wasNegated = true;
}
}
return wasNegated;
};
const bool op1WasNegated = lowerOperand(op1);
const bool op2WasNegated = lowerOperand(op2);
const bool op3WasNegated = lowerOperand(op3);
if (op1WasNegated)
{
if (op2WasNegated != op3WasNegated)
{
node->ChangeHWIntrinsicId(NI_AdvSimd_FusedMultiplyAddNegatedScalar);
}
else
{
node->ChangeHWIntrinsicId(NI_AdvSimd_FusedMultiplySubtractNegatedScalar);
}
}
else if (op2WasNegated != op3WasNegated)
{
node->ChangeHWIntrinsicId(NI_AdvSimd_FusedMultiplySubtractScalar);
}
}
//----------------------------------------------------------------------------------------------
// Lowering::LowerHWIntrinsic: Perform containment analysis for a hardware intrinsic node.
//
// Arguments:
// node - The hardware intrinsic node.
//
void Lowering::LowerHWIntrinsic(GenTreeHWIntrinsic* node)
{
assert(node->TypeGet() != TYP_SIMD32);
if (node->TypeGet() == TYP_SIMD12)
{
// GT_HWINTRINSIC node requiring to produce TYP_SIMD12 in fact
// produces a TYP_SIMD16 result
node->gtType = TYP_SIMD16;
}
NamedIntrinsic intrinsicId = node->GetHWIntrinsicId();
switch (intrinsicId)
{
case NI_Vector64_Create:
case NI_Vector128_Create:
{
// We don't directly support the Vector64.Create or Vector128.Create methods in codegen
// and instead lower them to other intrinsic nodes in LowerHWIntrinsicCreate so we expect
// that the node is modified to either not be a HWIntrinsic node or that it is no longer
// the same intrinsic as when it came in.
LowerHWIntrinsicCreate(node);
assert(!node->OperIsHWIntrinsic() || (node->GetHWIntrinsicId() != intrinsicId));
LowerNode(node);
return;
}
case NI_Vector64_Dot:
case NI_Vector128_Dot:
{
LowerHWIntrinsicDot(node);
return;
}
case NI_Vector64_op_Equality:
case NI_Vector128_op_Equality:
{
LowerHWIntrinsicCmpOp(node, GT_EQ);
return;
}
case NI_Vector64_op_Inequality:
case NI_Vector128_op_Inequality:
{
LowerHWIntrinsicCmpOp(node, GT_NE);
return;
}
case NI_AdvSimd_FusedMultiplyAddScalar:
LowerHWIntrinsicFusedMultiplyAddScalar(node);
break;
default:
break;
}
ContainCheckHWIntrinsic(node);
}
//----------------------------------------------------------------------------------------------
// Lowering::IsValidConstForMovImm: Determines if the given node can be replaced by a mov/fmov immediate instruction
//
// Arguments:
// node - The hardware intrinsic node.
//
// Returns:
// true if the node can be replaced by a mov/fmov immediate instruction; otherwise, false
//
// IMPORTANT:
// This check may end up modifying node->gtOp1 if it is a cast node that can be removed
bool Lowering::IsValidConstForMovImm(GenTreeHWIntrinsic* node)
{
assert((node->GetHWIntrinsicId() == NI_Vector64_Create) || (node->GetHWIntrinsicId() == NI_Vector128_Create) ||
(node->GetHWIntrinsicId() == NI_Vector64_CreateScalarUnsafe) ||
(node->GetHWIntrinsicId() == NI_Vector128_CreateScalarUnsafe) ||
(node->GetHWIntrinsicId() == NI_AdvSimd_DuplicateToVector64) ||
(node->GetHWIntrinsicId() == NI_AdvSimd_DuplicateToVector128) ||
(node->GetHWIntrinsicId() == NI_AdvSimd_Arm64_DuplicateToVector64) ||
(node->GetHWIntrinsicId() == NI_AdvSimd_Arm64_DuplicateToVector128));
assert(node->GetOperandCount() == 1);
GenTree* op1 = node->Op(1);
GenTree* castOp = nullptr;
// TODO-Casts: why don't we fold the casts? MinOpts?
if (varTypeIsIntegral(node->GetSimdBaseType()) && op1->OperIs(GT_CAST))
{
// We will sometimes get a cast around a constant value (such as for
// certain long constants) which would block the below containment.
// So we will temporarily check what the cast is from instead so we
// can catch those cases as well.
castOp = op1->AsCast()->CastOp();
op1 = castOp;
}
if (op1->IsCnsIntOrI())
{
const ssize_t dataValue = op1->AsIntCon()->gtIconVal;
if (comp->GetEmitter()->emitIns_valid_imm_for_movi(dataValue, emitActualTypeSize(node->GetSimdBaseType())))
{
if (castOp != nullptr)
{
// We found a containable immediate under
// a cast, so remove the cast from the LIR.
BlockRange().Remove(node->Op(1));
node->Op(1) = op1;
}
return true;
}
}
else if (op1->IsCnsFltOrDbl())
{
assert(varTypeIsFloating(node->GetSimdBaseType()));
assert(castOp == nullptr);
const double dataValue = op1->AsDblCon()->gtDconVal;
return comp->GetEmitter()->emitIns_valid_imm_for_fmov(dataValue);
}
return false;
}
//----------------------------------------------------------------------------------------------
// Lowering::LowerHWIntrinsicCmpOp: Lowers a Vector128 or Vector256 comparison intrinsic
//
// Arguments:
// node - The hardware intrinsic node.
// cmpOp - The comparison operation, currently must be GT_EQ or GT_NE
//
void Lowering::LowerHWIntrinsicCmpOp(GenTreeHWIntrinsic* node, genTreeOps cmpOp)
{
NamedIntrinsic intrinsicId = node->GetHWIntrinsicId();
CorInfoType simdBaseJitType = node->GetSimdBaseJitType();
var_types simdBaseType = node->GetSimdBaseType();
unsigned simdSize = node->GetSimdSize();
var_types simdType = Compiler::getSIMDTypeForSize(simdSize);
assert((intrinsicId == NI_Vector64_op_Equality) || (intrinsicId == NI_Vector64_op_Inequality) ||
(intrinsicId == NI_Vector128_op_Equality) || (intrinsicId == NI_Vector128_op_Inequality));
assert(varTypeIsSIMD(simdType));
assert(varTypeIsArithmetic(simdBaseType));
assert(simdSize != 0);
assert(node->gtType == TYP_BOOL);
assert((cmpOp == GT_EQ) || (cmpOp == GT_NE));
// We have the following (with the appropriate simd size and where the intrinsic could be op_Inequality):
// /--* op2 simd
// /--* op1 simd
// node = * HWINTRINSIC simd T op_Equality
GenTree* op1 = node->Op(1);
GenTree* op2 = node->Op(2);
NamedIntrinsic cmpIntrinsic;
switch (simdBaseType)
{
case TYP_BYTE:
case TYP_UBYTE:
case TYP_SHORT:
case TYP_USHORT:
case TYP_INT:
case TYP_UINT:
case TYP_FLOAT:
{
cmpIntrinsic = NI_AdvSimd_CompareEqual;
break;
}
case TYP_LONG:
case TYP_ULONG:
case TYP_DOUBLE:
{
cmpIntrinsic = (simdSize == 8) ? NI_AdvSimd_Arm64_CompareEqualScalar : NI_AdvSimd_Arm64_CompareEqual;
break;
}
default:
{
unreached();
}
}
GenTree* cmp = comp->gtNewSimdHWIntrinsicNode(simdType, op1, op2, cmpIntrinsic, simdBaseJitType, simdSize);
BlockRange().InsertBefore(node, cmp);
LowerNode(cmp);
if ((simdBaseType == TYP_FLOAT) && (simdSize == 12))
{
// For TYP_SIMD12 we don't want the upper bits to participate in the comparison. So, we will insert all ones
// into those bits of the result, "as if" the upper bits are equal. Then if all lower bits are equal, we get the
// expected all-ones result, and will get the expected 0's only where there are non-matching bits.
GenTree* idxCns = comp->gtNewIconNode(3, TYP_INT);
BlockRange().InsertAfter(cmp, idxCns);
GenTree* insCns = comp->gtNewIconNode(-1, TYP_INT);
BlockRange().InsertAfter(idxCns, insCns);
GenTree* tmp = comp->gtNewSimdAsHWIntrinsicNode(simdType, cmp, idxCns, insCns, NI_AdvSimd_Insert,
CORINFO_TYPE_INT, simdSize);
BlockRange().InsertAfter(insCns, tmp);
LowerNode(tmp);
cmp = tmp;
}
GenTree* msk =
comp->gtNewSimdHWIntrinsicNode(simdType, cmp, NI_AdvSimd_Arm64_MinAcross, CORINFO_TYPE_UBYTE, simdSize);
BlockRange().InsertAfter(cmp, msk);
LowerNode(msk);
GenTree* zroCns = comp->gtNewIconNode(0, TYP_INT);
BlockRange().InsertAfter(msk, zroCns);
GenTree* val =
comp->gtNewSimdAsHWIntrinsicNode(TYP_UBYTE, msk, zroCns, NI_AdvSimd_Extract, CORINFO_TYPE_UBYTE, simdSize);
BlockRange().InsertAfter(zroCns, val);
LowerNode(val);
zroCns = comp->gtNewIconNode(0, TYP_INT);
BlockRange().InsertAfter(val, zroCns);
node->ChangeOper(cmpOp);
node->gtType = TYP_INT;
node->AsOp()->gtOp1 = val;
node->AsOp()->gtOp2 = zroCns;
// The CompareEqual will set (condition is true) or clear (condition is false) all bits of the respective element
// The MinAcross then ensures we get either all bits set (all conditions are true) or clear (any condition is false)
// So, we need to invert the condition from the operation since we compare against zero
GenCondition cmpCnd = (cmpOp == GT_EQ) ? GenCondition::NE : GenCondition::EQ;
GenTree* cc = LowerNodeCC(node, cmpCnd);
node->gtType = TYP_VOID;
node->ClearUnusedValue();
LowerNode(node);
}
//----------------------------------------------------------------------------------------------
// Lowering::LowerHWIntrinsicCreate: Lowers a Vector64 or Vector128 Create call
//
// Performs the following transformations:
// 1. If all the arguments are constant (including the broadcast case), the vector
// will be loaded from the data section, or turned into Zero/AllBitsSet, if possible.
// 2. Non-constant broadcasts (argCnt == 1) are turned into DuplicateToVector intrinsics.
// 3. Remaining cases get a chain of "Insert"s, from the second element to the last, where
// the vector to be inserted into is created with CreateUnsafeScalar from the first element.
//
// Arguments:
// node - The hardware intrinsic node.
//
void Lowering::LowerHWIntrinsicCreate(GenTreeHWIntrinsic* node)
{
NamedIntrinsic intrinsicId = node->GetHWIntrinsicId();
var_types simdType = node->TypeGet();
CorInfoType simdBaseJitType = node->GetSimdBaseJitType();
var_types simdBaseType = node->GetSimdBaseType();
unsigned simdSize = node->GetSimdSize();
VectorConstant vecCns = {};
if ((simdSize == 8) && (simdType == TYP_DOUBLE))
{
// TODO-Cleanup: Struct retyping means we have the wrong type here. We need to
// manually fix it up so the simdType checks below are correct.
simdType = TYP_SIMD8;
}
assert(varTypeIsSIMD(simdType));
assert(varTypeIsArithmetic(simdBaseType));
assert(simdSize != 0);
size_t argCnt = node->GetOperandCount();
size_t cnsArgCnt = 0;
// These intrinsics are meant to set the same value to every element.
if ((argCnt == 1) && HandleArgForHWIntrinsicCreate(node->Op(1), 0, vecCns, simdBaseType))
{
// Now assign the rest of the arguments.
for (unsigned i = 1; i < simdSize / genTypeSize(simdBaseType); i++)
{
HandleArgForHWIntrinsicCreate(node->Op(1), i, vecCns, simdBaseType);
}
cnsArgCnt = 1;
}
else
{
for (unsigned i = 1; i <= argCnt; i++)
{
if (HandleArgForHWIntrinsicCreate(node->Op(i), i - 1, vecCns, simdBaseType))
{
cnsArgCnt++;
}
}
}
assert((argCnt == 1) || (argCnt == (simdSize / genTypeSize(simdBaseType))));
// Check if we have a cast that we can remove. Note that "IsValidConstForMovImm"
// will reset Op(1) if it finds such a cast, so we do not need to handle it here.
// TODO-Casts: why are casts from constants checked for here?
if ((argCnt == cnsArgCnt) && (argCnt == 1) && IsValidConstForMovImm(node))
{
// Set the cnsArgCnt to zero so we get lowered to a DuplicateToVector
// intrinsic, which will itself mark the node as contained.
cnsArgCnt = 0;
}
if (argCnt == cnsArgCnt)
{
for (GenTree* arg : node->Operands())
{
BlockRange().Remove(arg);
}
assert((simdSize == 8) || (simdSize == 16));
if (VectorConstantIsBroadcastedI64(vecCns, simdSize / 8))
{
// If we are a single constant or if all parts are the same, we might be able to optimize
// this even further for certain values, such as Zero or AllBitsSet.
if (vecCns.i64[0] == 0)
{
node->ResetHWIntrinsicId((simdSize == 8) ? NI_Vector64_get_Zero : NI_Vector128_get_Zero);
return;
}
else if (vecCns.i64[0] == -1)
{
node->ResetHWIntrinsicId((simdSize == 8) ? NI_Vector64_get_AllBitsSet : NI_Vector128_get_AllBitsSet);
return;
}
}
unsigned cnsSize = (simdSize == 12) ? 16 : simdSize;
unsigned cnsAlign = cnsSize;
var_types dataType = Compiler::getSIMDTypeForSize(simdSize);
UNATIVE_OFFSET cnum = comp->GetEmitter()->emitDataConst(&vecCns, cnsSize, cnsAlign, dataType);
CORINFO_FIELD_HANDLE hnd = comp->eeFindJitDataOffs(cnum);
GenTree* clsVarAddr = new (comp, GT_CLS_VAR_ADDR) GenTreeClsVar(GT_CLS_VAR_ADDR, TYP_I_IMPL, hnd, nullptr);
BlockRange().InsertBefore(node, clsVarAddr);