Add a transform for v1 & ~NegativeZero into -v1

Author: tannergooding

src/coreclr/jit/morph.cpp

@@ -10892,6 +10892,8 @@ GenTree* Compiler::fgOptimizeHWIntrinsic(GenTreeHWIntrinsic* node)
         // 2.((v1 ^ AllBitsSet) & v2) to VectorXxx.AndNot(v2, v1)
         // 3.(v1 & ~v2)               to VectorXxx.AndNot(v1, v2)
         // 4.(v1 & (v2 ^ AllBitsSet)) to VectorXxx.AndNot(v1, v2)
+        // 5.(v1 & ~NegativeZero)     to VectorXxx.Negate(v1)
+        // 6.(~NegativeZero & v2)     to VectorXxx.Negate(v2)
         case GT_AND:
         {
             GenTree*   op1 = node->Op(1);
@@ -10933,37 +10935,92 @@ GenTree* Compiler::fgOptimizeHWIntrinsic(GenTreeHWIntrinsic* node)
                     }
                 }
             }
-
-            if ((op == GT_NONE) && op2->OperIsHWIntrinsic())
+            else if (varTypeIsFloating(simdBaseType) && op1->IsVectorConst())
             {
-                GenTreeHWIntrinsic* hw     = op2->AsHWIntrinsic();
-                genTreeOps          hwOper = hw->HWOperGet();
+                GenTreeVecCon* vecCon = op1->AsVecCon();
 
-                if (hwOper == GT_NOT)
+                if (vecCon->IsBroadcast(retType, simdBaseType))
                 {
-                    // op1 & ~op2
-                    lhs = op1;
-                    rhs = hw->Op(1);
-                    op  = GT_AND_NOT;
+                    if (simdBaseType == TYP_FLOAT)
+                    {
+                        if (vecCon->gtSimdVal.u32[0] == 0x7FFFFFFF)
+                        {
+                            lhs = op2;
+                            op  = GT_NEG;
+                        }
+                    }
+                    else
+                    {
+                        assert(simdBaseType == TYP_DOUBLE);
+
+                        if (vecCon->gtSimdVal.u64[0] == 0x7FFFFFFFFFFFFFFF)
+                        {
+                            lhs = op2;
+                            op  = GT_NEG;
+                        }
+                    }
                 }
-                else if (hwOper == GT_XOR)
+            }
+
+            if (op == GT_NONE)
+            {
+                if (op2->OperIsHWIntrinsic())
                 {
-                    GenTree* hwOp1 = hw->Op(1);
-                    GenTree* hwOp2 = hw->Op(2);
+                    GenTreeHWIntrinsic* hw     = op2->AsHWIntrinsic();
+                    genTreeOps          hwOper = hw->HWOperGet();
 
-                    if (hwOp1->IsVectorAllBitsSet())
+                    if (hwOper == GT_NOT)
                     {
-                        // op1 & (AllBitsSet ^ op2)
+                        // op1 & ~op2
                         lhs = op1;
-                        rhs = hwOp2;
+                        rhs = hw->Op(1);
                         op  = GT_AND_NOT;
                     }
-                    else if (hwOp2->IsVectorAllBitsSet())
+                    else if (hwOper == GT_XOR)
                     {
-                        // op1 & (op2 ^ AllBitsSet)
-                        lhs = op1;
-                        rhs = hwOp1;
-                        op  = GT_AND_NOT;
+                        GenTree* hwOp1 = hw->Op(1);
+                        GenTree* hwOp2 = hw->Op(2);
+
+                        if (hwOp1->IsVectorAllBitsSet())
+                        {
+                            // op1 & (AllBitsSet ^ op2)
+                            lhs = op1;
+                            rhs = hwOp2;
+                            op  = GT_AND_NOT;
+                        }
+                        else if (hwOp2->IsVectorAllBitsSet())
+                        {
+                            // op1 & (op2 ^ AllBitsSet)
+                            lhs = op1;
+                            rhs = hwOp1;
+                            op  = GT_AND_NOT;
+                        }
+                    }
+                }
+                else if (varTypeIsFloating(simdBaseType) && op2->IsVectorConst())
+                {
+                    GenTreeVecCon* vecCon = op2->AsVecCon();
+
+                    if (vecCon->IsBroadcast(retType, simdBaseType))
+                    {
+                        if (simdBaseType == TYP_FLOAT)
+                        {
+                            if (vecCon->gtSimdVal.u32[0] == 0x7FFFFFFF)
+                            {
+                                lhs = op1;
+                                op  = GT_NEG;
+                            }
+                        }
+                        else
+                        {
+                            assert(simdBaseType == TYP_DOUBLE);
+
+                            if (vecCon->gtSimdVal.u64[0] == 0x7FFFFFFFFFFFFFFF)
+                            {
+                                lhs = op1;
+                                op  = GT_NEG;
+                            }
+                        }
                     }
                 }
             }
@@ -10973,6 +11030,17 @@ GenTree* Compiler::fgOptimizeHWIntrinsic(GenTreeHWIntrinsic* node)
                 break;
             }
 
+            if (rhs == nullptr)
+            {
+                // No need to filter side effects since we only have 1 operand
+                GenTree* resNode = gtNewSimdUnOpNode(op, retType, lhs, simdBaseJitType, simdSize);
+
+                DEBUG_DESTROY_NODE(node);
+                INDEBUG(resNode->gtDebugFlags |= GTF_DEBUG_NODE_MORPHED);
+
+                return resNode;
+            }
+
             // Filter out side effecting cases for several reasons:
             // 1. gtNewSimdBinOpNode may swap operand order.
             // 2. The code above will swap operand order.