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kunalspathak
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Add ARM64 encodings for groups IF_SVE_CE,CF (#98409)
* Add ARM64 encodings for groups IF_SVE_CE,CF * Move left-shifted integers into explicit types * Address review comments * Fix formatting errors * Fix a typo with register ID and add a scalable option for moving to and from predicate registers * Add shortcut for pmov with zero index * Fix formatting --------- Co-authored-by: Kunal Pathak <Kunal.Pathak@microsoft.com>
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‎src/coreclr/jit/codegenarm64test.cpp

+48
Original file line numberDiff line numberDiff line change
@@ -4733,6 +4733,54 @@ void CodeGen::genArm64EmitterUnitTestsSve()
47334733
theEmitter->emitIns_R_R_R(INS_sve_lsr, EA_SCALABLE, REG_V0, REG_P0, REG_V0, INS_OPTS_SCALABLE_S,
47344734
INS_SCALABLE_OPTS_WIDE); // LSR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D
47354735

4736+
// IF_SVE_CE_2A
4737+
theEmitter->emitIns_R_R(INS_sve_pmov, EA_SCALABLE, REG_P2, REG_V12, INS_OPTS_SCALABLE_B,
4738+
INS_SCALABLE_OPTS_TO_PREDICATE); // PMOV <Pd>.B, <Zn>
4739+
theEmitter->emitIns_R_R(INS_sve_pmov, EA_SCALABLE, REG_P7, REG_V2, INS_OPTS_SCALABLE_H,
4740+
INS_SCALABLE_OPTS_TO_PREDICATE); // PMOV <Pd>.H, <Zn>[0]
4741+
4742+
// IF_SVE_CE_2B
4743+
theEmitter->emitIns_R_R_I(INS_sve_pmov, EA_SCALABLE, REG_P15, REG_V7, 7, INS_OPTS_SCALABLE_D,
4744+
INS_SCALABLE_OPTS_TO_PREDICATE); // PMOV <Pd>.D, <Zn>[<imm>]
4745+
theEmitter->emitIns_R_R_I(INS_sve_pmov, EA_SCALABLE, REG_P7, REG_V16, 0, INS_OPTS_SCALABLE_D,
4746+
INS_SCALABLE_OPTS_TO_PREDICATE); // PMOV <Pd>.D, <Zn>[<imm>]
4747+
4748+
// IF_SVE_CE_2C
4749+
theEmitter->emitIns_R_R_I(INS_sve_pmov, EA_SCALABLE, REG_P0, REG_V31, 1, INS_OPTS_SCALABLE_H,
4750+
INS_SCALABLE_OPTS_TO_PREDICATE); // PMOV <Pd>.H, <Zn>[<imm>]
4751+
theEmitter->emitIns_R_R_I(INS_sve_pmov, EA_SCALABLE, REG_V1, REG_P1, 0, INS_OPTS_SCALABLE_H,
4752+
INS_SCALABLE_OPTS_TO_PREDICATE); // PMOV <Pd>.H, <Zn>[<imm>]
4753+
4754+
// IF_SVE_CE_2D
4755+
theEmitter->emitIns_R_R_I(INS_sve_pmov, EA_SCALABLE, REG_P3, REG_V9, 3, INS_OPTS_SCALABLE_S,
4756+
INS_SCALABLE_OPTS_TO_PREDICATE); // PMOV <Pd>.S, <Zn>[<imm>]
4757+
theEmitter->emitIns_R_R_I(INS_sve_pmov, EA_SCALABLE, REG_P10, REG_V4, 0, INS_OPTS_SCALABLE_S,
4758+
INS_SCALABLE_OPTS_TO_PREDICATE); // PMOV <Pd>.S, <Zn>[<imm>]
4759+
4760+
// IF_SVE_CF_2A
4761+
theEmitter->emitIns_R_R(INS_sve_pmov, EA_SCALABLE, REG_V11, REG_P12, INS_OPTS_SCALABLE_B,
4762+
INS_SCALABLE_OPTS_TO_VECTOR); // PMOV <Zd>, <Pn>.B
4763+
theEmitter->emitIns_R_R(INS_sve_pmov, EA_SCALABLE, REG_V2, REG_P7, INS_OPTS_SCALABLE_S,
4764+
INS_SCALABLE_OPTS_TO_VECTOR); // PMOV <Zd>[0], <Pn>.S
4765+
4766+
// IF_SVE_CF_2B
4767+
theEmitter->emitIns_R_R_I(INS_sve_pmov, EA_SCALABLE, REG_V6, REG_P8, 7, INS_OPTS_SCALABLE_D,
4768+
INS_SCALABLE_OPTS_TO_VECTOR); // PMOV <Zd>[<imm>], <Pn>.D
4769+
theEmitter->emitIns_R_R_I(INS_sve_pmov, EA_SCALABLE, REG_V9, REG_P7, 0, INS_OPTS_SCALABLE_D,
4770+
INS_SCALABLE_OPTS_TO_VECTOR); // PMOV <Zd>[<imm>], <Pn>.D
4771+
4772+
// IF_SVE_CF_2C
4773+
theEmitter->emitIns_R_R_I(INS_sve_pmov, EA_SCALABLE, REG_V8, REG_P4, 1, INS_OPTS_SCALABLE_H,
4774+
INS_SCALABLE_OPTS_TO_VECTOR); // PMOV <Zd>[<imm>], <Pn>.H
4775+
theEmitter->emitIns_R_R_I(INS_sve_pmov, EA_SCALABLE, REG_V5, REG_P9, 0, INS_OPTS_SCALABLE_H,
4776+
INS_SCALABLE_OPTS_TO_VECTOR); // PMOV <Zd>[<imm>], <Pn>.H
4777+
4778+
// IF_SVE_CF_2D
4779+
theEmitter->emitIns_R_R_I(INS_sve_pmov, EA_SCALABLE, REG_V14, REG_P2, 3, INS_OPTS_SCALABLE_S,
4780+
INS_SCALABLE_OPTS_TO_VECTOR); // PMOV <Zd>[<imm>], <Pn>.S
4781+
theEmitter->emitIns_R_R_I(INS_sve_pmov, EA_SCALABLE, REG_V3, REG_P15, 0, INS_OPTS_SCALABLE_S,
4782+
INS_SCALABLE_OPTS_TO_VECTOR); // PMOV <Zd>[<imm>], <Pn>.S
4783+
47364784
// IF_SVE_CJ_2A
47374785
theEmitter->emitIns_R_R(INS_sve_rev, EA_SCALABLE, REG_P1, REG_P2,
47384786
INS_OPTS_SCALABLE_B); // REV <Pd>.<T>, <Pn>.<T>

‎src/coreclr/jit/emitarm64.cpp

+254
Original file line numberDiff line numberDiff line change
@@ -1144,6 +1144,52 @@ void emitter::emitInsSanityCheck(instrDesc* id)
11441144
assert(isValidUimm4From1(emitGetInsSC(id)));
11451145
break;
11461146

1147+
case IF_SVE_CE_2A: // ................ ......nnnnn.DDDD -- SVE move predicate from vector
1148+
assert(isPredicateRegister(id->idReg1())); // DDDD
1149+
assert(isVectorRegister(id->idReg2())); // nnnnn
1150+
break;
1151+
1152+
case IF_SVE_CE_2B: // .........i...ii. ......nnnnn.DDDD -- SVE move predicate from vector
1153+
assert(isPredicateRegister(id->idReg1())); // DDDD
1154+
assert(isVectorRegister(id->idReg2())); // nnnnn
1155+
assert(isValidUimm<3>(emitGetInsSC(id)));
1156+
break;
1157+
1158+
case IF_SVE_CE_2C: // ..............i. ......nnnnn.DDDD -- SVE move predicate from vector
1159+
assert(isPredicateRegister(id->idReg1())); // DDDD
1160+
assert(isVectorRegister(id->idReg2())); // nnnnn
1161+
assert(isValidUimm<1>(emitGetInsSC(id))); // i
1162+
break;
1163+
1164+
case IF_SVE_CE_2D: // .............ii. ......nnnnn.DDDD -- SVE move predicate from vector
1165+
assert(isPredicateRegister(id->idReg1())); // DDDD
1166+
assert(isVectorRegister(id->idReg2())); // nnnnn
1167+
assert(isValidUimm<3>(emitGetInsSC(id))); // ii
1168+
break;
1169+
1170+
case IF_SVE_CF_2A: // ................ .......NNNNddddd -- SVE move predicate into vector
1171+
assert(isVectorRegister(id->idReg1())); // ddddd
1172+
assert(isPredicateRegister(id->idReg2())); // NNNN
1173+
break;
1174+
1175+
case IF_SVE_CF_2B: // .........i...ii. .......NNNNddddd -- SVE move predicate into vector
1176+
assert(isVectorRegister(id->idReg1())); // ddddd
1177+
assert(isPredicateRegister(id->idReg2())); // NNNN
1178+
assert(isValidUimm<3>(emitGetInsSC(id)));
1179+
break;
1180+
1181+
case IF_SVE_CF_2C: // ..............i. .......NNNNddddd -- SVE move predicate into vector
1182+
assert(isVectorRegister(id->idReg1())); // ddddd
1183+
assert(isPredicateRegister(id->idReg2())); // NNNN
1184+
assert(isValidUimm<1>(emitGetInsSC(id))); // i
1185+
break;
1186+
1187+
case IF_SVE_CF_2D: // .............ii. .......NNNNddddd -- SVE move predicate into vector
1188+
assert(isVectorRegister(id->idReg1())); // ddddd
1189+
assert(isPredicateRegister(id->idReg2())); // NNNN
1190+
assert(isValidUimm<2>(emitGetInsSC(id))); // ii
1191+
break;
1192+
11471193
case IF_SVE_CI_3A: // ........xx..MMMM .......NNNN.DDDD -- SVE permute predicate elements
11481194
elemsize = id->idOpSize();
11491195
assert(insOptsScalableStandard(id->idInsOpt()));
@@ -8775,6 +8821,30 @@ void emitter::emitIns_R_R(instruction ins,
87758821
}
87768822
break;
87778823

8824+
case INS_sve_pmov:
8825+
if (opt != INS_OPTS_SCALABLE_B)
8826+
{
8827+
assert(insOptsScalableStandard(opt));
8828+
return emitIns_R_R_I(INS_sve_pmov, attr, reg1, reg2, 0, opt, sopt);
8829+
}
8830+
if (sopt == INS_SCALABLE_OPTS_TO_PREDICATE)
8831+
{
8832+
assert(isPredicateRegister(reg1));
8833+
assert(isVectorRegister(reg2));
8834+
fmt = IF_SVE_CE_2A;
8835+
}
8836+
else if (sopt == INS_SCALABLE_OPTS_TO_VECTOR)
8837+
{
8838+
assert(isVectorRegister(reg1));
8839+
assert(isPredicateRegister(reg2));
8840+
fmt = IF_SVE_CF_2A;
8841+
}
8842+
else
8843+
{
8844+
assert(!"invalid instruction");
8845+
}
8846+
break;
8847+
87788848
case INS_sve_movs:
87798849
{
87808850
assert(opt == INS_OPTS_SCALABLE_B);
@@ -9817,6 +9887,57 @@ void emitter::emitIns_R_R_I(instruction ins,
98179887
fmt = IF_SVE_BB_2A;
98189888
break;
98199889

9890+
case INS_sve_pmov:
9891+
if (sopt == INS_SCALABLE_OPTS_TO_PREDICATE)
9892+
{
9893+
assert(isPredicateRegister(reg1));
9894+
assert(isVectorRegister(reg2));
9895+
switch (opt)
9896+
{
9897+
case INS_OPTS_SCALABLE_D:
9898+
assert(isValidUimm<3>(imm));
9899+
fmt = IF_SVE_CE_2B;
9900+
break;
9901+
case INS_OPTS_SCALABLE_S:
9902+
assert(isValidUimm<2>(imm));
9903+
fmt = IF_SVE_CE_2D;
9904+
break;
9905+
case INS_OPTS_SCALABLE_H:
9906+
assert(isValidUimm<1>(imm));
9907+
fmt = IF_SVE_CE_2C;
9908+
break;
9909+
default:
9910+
unreached();
9911+
}
9912+
}
9913+
else if (sopt == INS_SCALABLE_OPTS_TO_VECTOR)
9914+
{
9915+
assert(isVectorRegister(reg1));
9916+
assert(isPredicateRegister(reg2));
9917+
switch (opt)
9918+
{
9919+
case INS_OPTS_SCALABLE_D:
9920+
assert(isValidUimm<3>(imm));
9921+
fmt = IF_SVE_CF_2B;
9922+
break;
9923+
case INS_OPTS_SCALABLE_S:
9924+
assert(isValidUimm<2>(imm));
9925+
fmt = IF_SVE_CF_2D;
9926+
break;
9927+
case INS_OPTS_SCALABLE_H:
9928+
assert(isValidUimm<1>(imm));
9929+
fmt = IF_SVE_CF_2C;
9930+
break;
9931+
default:
9932+
unreached();
9933+
}
9934+
}
9935+
else
9936+
{
9937+
unreached();
9938+
}
9939+
break;
9940+
98209941
case INS_sve_sqrshrn:
98219942
case INS_sve_sqrshrun:
98229943
case INS_sve_uqrshrn:
@@ -19596,6 +19717,10 @@ void emitter::emitIns_Call(EmitCallType callType,
1959619717

1959719718
case IF_SVE_CZ_4A_A:
1959819719
case IF_SVE_CZ_4A_L:
19720+
case IF_SVE_CE_2A:
19721+
case IF_SVE_CE_2B:
19722+
case IF_SVE_CE_2C:
19723+
case IF_SVE_CE_2D:
1959919724
case IF_SVE_CF_2A:
1960019725
case IF_SVE_CF_2B:
1960119726
case IF_SVE_CF_2C:
@@ -23841,6 +23966,68 @@ BYTE* emitter::emitOutput_InstrSve(BYTE* dst, instrDesc* id)
2384123966
dst += emitOutput_Instr(dst, code);
2384223967
break;
2384323968

23969+
case IF_SVE_CE_2A: // ................ ......nnnnn.DDDD -- SVE move predicate from vector
23970+
code = emitInsCodeSve(ins, fmt);
23971+
code |= insEncodeReg_P_3_to_0(id->idReg1()); // DDDD
23972+
code |= insEncodeReg_V_9_to_5(id->idReg2()); // nnnnn
23973+
dst += emitOutput_Instr(dst, code);
23974+
break;
23975+
23976+
case IF_SVE_CE_2B: // .........i...ii. ......nnnnn.DDDD -- SVE move predicate from vector
23977+
code = emitInsCodeSve(ins, fmt);
23978+
code |= insEncodeReg_P_3_to_0(id->idReg1()); // DDDD
23979+
code |= insEncodeReg_V_9_to_5(id->idReg2()); // nnnnn
23980+
code |= insEncodeSplitUimm<22, 22, 18, 17>(emitGetInsSC(id)); // i...ii
23981+
dst += emitOutput_Instr(dst, code);
23982+
break;
23983+
23984+
case IF_SVE_CE_2C: // ..............i. ......nnnnn.DDDD -- SVE move predicate from vector
23985+
code = emitInsCodeSve(ins, fmt);
23986+
code |= insEncodeReg_P_3_to_0(id->idReg1()); // DDDD
23987+
code |= insEncodeReg_V_9_to_5(id->idReg2()); // nnnnn
23988+
code |= insEncodeUimm<17, 17>(emitGetInsSC(id)); // i
23989+
dst += emitOutput_Instr(dst, code);
23990+
break;
23991+
23992+
case IF_SVE_CE_2D: // .............ii. ......nnnnn.DDDD -- SVE move predicate from vector
23993+
code = emitInsCodeSve(ins, fmt);
23994+
code |= insEncodeReg_P_3_to_0(id->idReg1()); // DDDD
23995+
code |= insEncodeReg_V_9_to_5(id->idReg2()); // nnnnn
23996+
code |= insEncodeUimm<18, 17>(emitGetInsSC(id)); // ii
23997+
dst += emitOutput_Instr(dst, code);
23998+
break;
23999+
24000+
case IF_SVE_CF_2A: // ................ .......NNNNddddd -- SVE move predicate into vector
24001+
code = emitInsCodeSve(ins, fmt);
24002+
code |= insEncodeReg_V_4_to_0(id->idReg1()); // ddddd
24003+
code |= insEncodeReg_P_8_to_5(id->idReg2()); // NNNN
24004+
dst += emitOutput_Instr(dst, code);
24005+
break;
24006+
24007+
case IF_SVE_CF_2B: // .........i...ii. .......NNNNddddd -- SVE move predicate into vector
24008+
code = emitInsCodeSve(ins, fmt);
24009+
code |= insEncodeReg_V_4_to_0(id->idReg1()); // ddddd
24010+
code |= insEncodeReg_P_8_to_5(id->idReg2()); // NNNN
24011+
code |= insEncodeSplitUimm<22, 22, 18, 17>(emitGetInsSC(id)); // i...ii
24012+
dst += emitOutput_Instr(dst, code);
24013+
break;
24014+
24015+
case IF_SVE_CF_2C: // ..............i. .......NNNNddddd -- SVE move predicate into vector
24016+
code = emitInsCodeSve(ins, fmt);
24017+
code |= insEncodeReg_V_4_to_0(id->idReg1()); // ddddd
24018+
code |= insEncodeReg_P_8_to_5(id->idReg2()); // NNNN
24019+
code |= insEncodeUimm<17, 17>(emitGetInsSC(id)); // i
24020+
dst += emitOutput_Instr(dst, code);
24021+
break;
24022+
24023+
case IF_SVE_CF_2D: // .............ii. .......NNNNddddd -- SVE move predicate into vector
24024+
code = emitInsCodeSve(ins, fmt);
24025+
code |= insEncodeReg_V_4_to_0(id->idReg1()); // ddddd
24026+
code |= insEncodeReg_P_8_to_5(id->idReg2()); // NNNN
24027+
code |= insEncodeUimm<18, 17>(emitGetInsSC(id)); // ii
24028+
dst += emitOutput_Instr(dst, code);
24029+
break;
24030+
2384424031
case IF_SVE_CI_3A: // ........xx..MMMM .......NNNN.DDDD -- SVE permute predicate elements
2384524032
code = emitInsCodeSve(ins, fmt);
2384624033
code |= insEncodeReg_P_3_to_0(id->idReg1()); // DDDD
@@ -25733,6 +25920,18 @@ void emitter::emitDispReg(regNumber reg, emitAttr attr, bool addComma)
2573325920
emitDispComma();
2573425921
}
2573525922

25923+
//------------------------------------------------------------------------
25924+
// emitDispSveReg: Display a scalable vector register name
25925+
//
25926+
void emitter::emitDispSveReg(regNumber reg, bool addComma)
25927+
{
25928+
assert(isVectorRegister(reg));
25929+
printf(emitSveRegName(reg));
25930+
25931+
if (addComma)
25932+
emitDispComma();
25933+
}
25934+
2573625935
//------------------------------------------------------------------------
2573725936
// emitDispSveReg: Display a scalable vector register name with an arrangement suffix
2573825937
//
@@ -25751,6 +25950,16 @@ void emitter::emitDispSveReg(regNumber reg, insOpts opt, bool addComma)
2575125950
emitDispComma();
2575225951
}
2575325952

25953+
//------------------------------------------------------------------------
25954+
// emitDispSveRegIndex: Display a scalable vector register with indexed element
25955+
//
25956+
void emitter::emitDispSveRegIndex(regNumber reg, ssize_t index, bool addComma)
25957+
{
25958+
assert(isVectorRegister(reg));
25959+
printf(emitSveRegName(reg));
25960+
emitDispElementIndex(index, addComma);
25961+
}
25962+
2575425963
//------------------------------------------------------------------------
2575525964
// emitDispVectorReg: Display a SIMD vector register name with an arrangement suffix
2575625965
//
@@ -27947,6 +28156,39 @@ void emitter::emitDispInsHelp(
2794728156
emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm
2794828157
break;
2794928158

28159+
case IF_SVE_CE_2A: // ................ ......nnnnn.DDDD -- SVE move predicate from vector
28160+
emitDispPredicateReg(id->idReg1(), insGetPredicateType(fmt), INS_OPTS_SCALABLE_B, true); // DDDD
28161+
emitDispSveReg(id->idReg2(), false); // nnnnn
28162+
break;
28163+
case IF_SVE_CE_2B: // .........i...ii. ......nnnnn.DDDD -- SVE move predicate from vector
28164+
emitDispPredicateReg(id->idReg1(), insGetPredicateType(fmt), INS_OPTS_SCALABLE_D, true); // DDDD
28165+
emitDispSveRegIndex(id->idReg2(), emitGetInsSC(id), false); // nnnnn
28166+
break;
28167+
case IF_SVE_CE_2C: // ..............i. ......nnnnn.DDDD -- SVE move predicate from vector
28168+
emitDispPredicateReg(id->idReg1(), insGetPredicateType(fmt), INS_OPTS_SCALABLE_H, true); // DDDD
28169+
emitDispSveRegIndex(id->idReg2(), emitGetInsSC(id), false); // nnnnn
28170+
break;
28171+
case IF_SVE_CE_2D: // .............ii. ......nnnnn.DDDD -- SVE move predicate from vector
28172+
emitDispPredicateReg(id->idReg1(), insGetPredicateType(fmt), INS_OPTS_SCALABLE_S, true); // DDDD
28173+
emitDispSveRegIndex(id->idReg2(), emitGetInsSC(id), false); // nnnnn
28174+
break;
28175+
case IF_SVE_CF_2A: // ................ .......NNNNddddd -- SVE move predicate into vector
28176+
emitDispSveReg(id->idReg1(), true); // ddddd
28177+
emitDispPredicateReg(id->idReg2(), insGetPredicateType(fmt), INS_OPTS_SCALABLE_B, false); // NNNN
28178+
break;
28179+
case IF_SVE_CF_2B: // .........i...ii. .......NNNNddddd -- SVE move predicate into vector
28180+
emitDispSveRegIndex(id->idReg1(), emitGetInsSC(id), true); // ddddd
28181+
emitDispPredicateReg(id->idReg2(), insGetPredicateType(fmt), INS_OPTS_SCALABLE_D, false); // NNNN
28182+
break;
28183+
case IF_SVE_CF_2C: // ..............i. .......NNNNddddd -- SVE move predicate into vector
28184+
emitDispSveRegIndex(id->idReg1(), emitGetInsSC(id), true); // ddddd
28185+
emitDispPredicateReg(id->idReg2(), insGetPredicateType(fmt), INS_OPTS_SCALABLE_H, false); // NNNN
28186+
break;
28187+
case IF_SVE_CF_2D: // .............ii. .......NNNNddddd -- SVE move predicate into vector
28188+
emitDispSveRegIndex(id->idReg1(), emitGetInsSC(id), true); // ddddd
28189+
emitDispPredicateReg(id->idReg2(), insGetPredicateType(fmt), INS_OPTS_SCALABLE_S, false); // NNNN
28190+
break;
28191+
2795028192
// <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
2795128193
case IF_SVE_CI_3A: // ........xx..MMMM .......NNNN.DDDD -- SVE permute predicate elements
2795228194
emitDispPredicateReg(id->idReg1(), insGetPredicateType(fmt, 1), id->idInsOpt(), true); // DDDD
@@ -31763,6 +32005,18 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
3176332005
result.insLatency = PERFSCORE_LATENCY_2C;
3176432006
break;
3176532007

32008+
case IF_SVE_CE_2A: // ................ ......nnnnn.DDDD -- SVE move predicate from vector
32009+
case IF_SVE_CE_2B: // .........i...ii. ......nnnnn.DDDD -- SVE move predicate from vector
32010+
case IF_SVE_CE_2C: // ..............i. ......nnnnn.DDDD -- SVE move predicate from vector
32011+
case IF_SVE_CE_2D: // .............ii. ......nnnnn.DDDD -- SVE move predicate from vector
32012+
case IF_SVE_CF_2A: // ................ .......NNNNddddd -- SVE move predicate into vector
32013+
case IF_SVE_CF_2B: // .........i...ii. .......NNNNddddd -- SVE move predicate into vector
32014+
case IF_SVE_CF_2C: // ..............i. .......NNNNddddd -- SVE move predicate into vector
32015+
case IF_SVE_CF_2D: // .............ii. .......NNNNddddd -- SVE move predicate into vector
32016+
result.insThroughput = PERFSCORE_THROUGHPUT_140C; // @ToDo currently undocumented
32017+
result.insLatency = PERFSCORE_LATENCY_140C;
32018+
break;
32019+
3176632020
case IF_SVE_CI_3A: // ........xx..MMMM .......NNNN.DDDD -- SVE permute predicate elements
3176732021
case IF_SVE_CJ_2A: // ........xx...... .......NNNN.DDDD -- SVE reverse predicate elements
3176832022
case IF_SVE_CK_2A: // ................ .......NNNN.DDDD -- SVE unpack predicate elements

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