amend the code for CRs.

Author: shushanhf

src/coreclr/jit/codegencommon.cpp

@@ -4093,10 +4093,10 @@ void CodeGen::genEnregisterOSRArgsAndLocals()
         // We need to determine the frame-pointer relative
         // offset for this variable in the osr frame.
         //
-        // First there is no need to ajust stkOffs
-        // as it relative to sp within Tier0 frame
+        // Note: there is no need to adjust stkOffs
+        // as it is relative to sp within Tier0 frame.
 
-        // then add the OSR frame size
+        // Add the OSR frame size.
         //
         const int osrFrameSize = genTotalFrameSize();
 
@@ -4116,7 +4116,7 @@ void CodeGen::genEnregisterOSRArgsAndLocals()
 
         genInstrWithConstant(ins_Load(lclTyp), size, varDsc->GetRegNum(), genFramePointerReg(), offset, initReg);
         *pInitRegZeroed = false;
-#endif // TARGET_LOONGARCH64 || TARGET_RISCV64
+#endif // TARGET_LOONGARCH64 || TARGET_RISCV64 || TARGET_ARM64
     }
 }
 

src/coreclr/jit/codegenloongarch64.cpp

@@ -691,7 +691,7 @@ void CodeGen::genRestoreCalleeSavedRegistersHelp(regMaskTP regsToRestoreMask, in
  *      |-----------------------|
  *      |        PSP slot       | // 8 bytes (omitted in NativeAOT ABI)
  *      |-----------------------|
- *      |Callee saved registers | // multiple of 8 bytes, not includting FP/RA
+ *      |Callee saved registers | // multiple of 8 bytes, not including FP/RA
  *      |-----------------------|
  *      |      Saved FP, RA     | // 16 bytes
  *      |-----------------------|

src/coreclr/jit/codegenriscv64.cpp

@@ -787,7 +787,7 @@ void CodeGen::genRestoreCalleeSavedRegistersHelp(regMaskTP regsToRestoreMask, in
  *      |-----------------------|
  *      ~  alignment padding    ~ // To make the whole frame 16 byte aligned
  *      |-----------------------|
- *      |Callee saved registers | // multiple of 8 bytes, not includting FP/RA
+ *      |Callee saved registers | // multiple of 8 bytes, not including FP/RA
  *      |-----------------------|
  *      |      Saved FP, RA     | // 16 bytes
  *      |-----------------------|

src/coreclr/jit/lclvars.cpp

@@ -5707,15 +5707,15 @@ void Compiler::lvaFixVirtualFrameOffsets()
     }
 #endif // !TARGET_LOONGARCH64 || !TARGET_RISCV64
 
+#if defined(TARGET_AMD64)
     if (opts.IsOSR())
     {
-#if defined(TARGET_AMD64)
         // Stack offset includes Tier0 frame.
         //
         JITDUMP("--- delta bump %d for OSR + Tier0 frame\n", info.compPatchpointInfo->TotalFrameSize());
         delta += info.compPatchpointInfo->TotalFrameSize();
-#endif // TARGET_AMD64
     }
+#endif // TARGET_AMD64
 
     JITDUMP("--- virtual stack offset to actual stack offset delta is %d\n", delta);