Arm64: Improve code generation for Vector<T> comparision

[CarolEidt]

An example from ConsoleMandel:
Source:

while (increment != Vector<int>.Zero);

Generated code:

            dup     v20.4s, wzr
            cmeq    v21.4s, v19.4s, v20.4s
            uminv   v21.16b, v21.16b
            mov     w0, v21.b[0]
            eor     w0, w0, #1
            and     w0, w0, #1

            cbnz    w0, G_M3984_IG05

I believe that umaxv could be used for the != case. Also, if the result of the comparison is used in a branch, we shouldn't have to produce the precise 1 or 0.

category:cq
theme:vector-codegen
skill-level:intermediate
cost:medium

[AndyAyersMS]

@CarolEidt @kunalspathak is this something we should put into .NET 5?

[tannergooding]

Some of this may naturally improve with the changes I did for #35421 and the follow up PR I'll be submitting to handle cases like op_Equality and op_Inequality.

[AndyAyersMS]

Ok, will put in 5.0, we can revisit later if this is optimistic.

[BruceForstall]

@tannergooding @CarolEidt Is there any work left here? Should the issue remain in 5.0?

[kunalspathak]

In one of my previous PRs Tamar pointed out in #37624 (comment) that addp or uminp is cheaper than uminv, so may be that's the minimum we should do. If @tannergooding is busy, I can take some time to do it.

[BruceForstall]

I'm moving this to Future.

[kunalspathak]

@EgorBo - can you double check if #65632 handles this pattern?

[EgorBo]

Just checked - yes, it does