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Test failure: System.AccessViolationException: Attempted to read or write protected memory. This is often an indication that other memory is corrupt #36198

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v-haren opened this issue May 11, 2020 · 5 comments · Fixed by #36226
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area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI JitStress CLR JIT issues involving JIT internal stress modes
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@v-haren
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v-haren commented May 11, 2020

failed in job: runtime-coreclr jitstressregs 20200510.1

failed tests:
JIT\HardwareIntrinsics\X86\Regression\GitHub_21666\GitHub_21666_ro\GitHub_21666_ro.cmd
JIT\HardwareIntrinsics\X86\Regression\GitHub_21666\GitHub_21666_r\GitHub_21666_r.cmd
JIT/HardwareIntrinsics/X86/Regression/GitHub_21666/GitHub_21666_r/GitHub_21666_r.sh
JIT/HardwareIntrinsics/X86/Regression/GitHub_21666/GitHub_21666_ro/GitHub_21666_ro.sh

Error message

Fatal error. System.AccessViolationException: Attempted to read or write protected memory. This is often an indication that other memory is corrupt.
 at GitHub_21666.GitHub_21666.TestByteContainment()
 at GitHub_21666.GitHub_21666.Main(System.String[])
/home/helixbot/work/AA5808CF/w/C5820A5E/e/JIT/HardwareIntrinsics/X86/Regression/GitHub_21666/GitHub_21666_r/GitHub_21666_r.sh: line 312: 22740 Aborted $LAUNCHER $ExePath "${CLRTestExecutionArguments[@]}"

Return code: 1
Raw output file: /home/helixbot/work/AA5808CF/w/C5820A5E/e/JIT/HardwareIntrinsics/Reports/JIT.HardwareIntrinsics/X86/Regression/GitHub_21666/GitHub_21666_r/GitHub_21666_r.output.txt
Raw output:
BEGIN EXECUTION
/home/helixbot/work/AA5808CF/p/corerun GitHub_21666_r.dll ''

Writing minidump to file /home/helixbot/dotnetbuild/dumps/coredump.22740.dmp
Written 52936704 bytes (12924 pages) to core file
Dump successfully written
Expected: 100
Actual: 134
END EXECUTION - FAILED
Test Harness Exitcode is : 1
To run the test:
> set CORE_ROOT=/home/helixbot/work/AA5808CF/p
> /home/helixbot/work/AA5808CF/w/C5820A5E/e/JIT/HardwareIntrinsics/X86/Regression/GitHub_21666/GitHub_21666_r/GitHub_21666_r.sh
Expected: True
Actual: False


Stack trace
   at JIT_HardwareIntrinsics._X86_Regression_GitHub_21666_GitHub_21666_r_GitHub_21666_r_._X86_Regression_GitHub_21666_GitHub_21666_r_GitHub_21666_r_sh() in /__w/1/s/artifacts/tests/coreclr/Linux.x64.Checked/TestWrappers/JIT.HardwareIntrinsics/JIT.HardwareIntrinsics.XUnitWrapper.cs:line 14108
@v-haren v-haren added JitStress CLR JIT issues involving JIT internal stress modes area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI labels May 11, 2020
@Dotnet-GitSync-Bot Dotnet-GitSync-Bot added the untriaged New issue has not been triaged by the area owner label May 11, 2020
@tannergooding
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Looking...

@BruceForstall
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From CoreCLR Linux x64 Checked jitstressregs4 @ Ubuntu.1804.Amd64.Open

export COMPlus_TieredCompilation=0
export COMPlus_JitStressRegs=4

@BruceForstall BruceForstall added this to the 5.0 milestone May 11, 2020
@BruceForstall BruceForstall removed the untriaged New issue has not been triaged by the area owner label May 11, 2020
@BruceForstall
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cc @CarolEidt @echesakovMSFT @kunalspathak

@tannergooding
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This is an issue in LinearScan::BuildHWIntrinsic and was introduced in #35421.

Basically, we were missing a scenario where the intrinsic is RMW, op2 is contained, and it is producing a non-SIMD result, in which case the operand needs to be delay free since the address and the destination (e.g. Crc32)

We don't need this when the node produces a SIMD result since the destination will be an XMM register and the address will be in a GP register. I've got a fix locally and am validating it now. A PR should be up shortly.

@CarolEidt
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Thanks @tannergooding for tracking this down!

@ghost ghost closed this as completed in #36226 May 11, 2020
@ghost ghost locked as resolved and limited conversation to collaborators Dec 9, 2020
This issue was closed.
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