[LSRA] Add support for allocating consecutive registers

[CarolEidt]

This is currently supported in a limited form for Arm32 double registers, which must be an even/odd pair. However, this support is not well structured, and penalizes the common path that requires only a single register.
In order to support the Arm64 LoadPairVector intrinsics (#39243) intrinsics that would correspond to LD1-LD4, ST1-ST4 instruction, we need the ability to allocate consecutive vector registers, and we don't want to penalize the common path for this case.
One option would be to templatize the allocation methods such that the ones supporting consecutive registers would only be called when required.
Related: issue #8758 would presumably be addressed by such an approach.

category:proposal
theme:register-allocator
skill-level:expert
cost:large
impact:medium

[ghost]

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[echesakov]

@CarolEidt Small correction: we need consecutive vector registers allocation for Arm64 intrinsics that would correspond to LD1-LD4, ST1-ST4 instruction not for LoadPairVector/StorePair since the latter can operate on an arbitrary pair of SIMD registers.

[CarolEidt]

@echesakovMSFT - thanks for clarifying!

[kunalspathak]

I don't think we will do this in .NET 6.0. Moving to future.

[kunalspathak]

Completed by #80297. Note that the arm scenarios are different because the consecutive registers represent a single double variable but for other common cases like arm64's tbl/tbx/ld2~ld4, st2~st4 needs consecutive registers for independent intervals which is handled by #80297.