JIT: Consider reordering loads on ARM64 to make them amenable to ldp optimization

[jakobbotsch]

E.g. see the "after" codegen in #92710 (comment). It shouldn't be hard to add an optimization during lowering that tries to reorder related stores like this to make them amenable to the ldp peephole.

cc @dotnet/jit-contrib

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Issue Details

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E.g. see the "after" codegen in #92710 (comment). It shouldn't be hard to add an optimization during lowering that tries to reorder related stores like this to make them amenable to the ldp peephole.

cc @dotnet/jit-contrib

Author:	jakobbotsch
Assignees:	-
Labels:	area-CodeGen-coreclr, untriaged
Milestone:	-

[BruceForstall]

Or maybe the ldr=>ldp peephole could look back more than one instruction? The trick would be to avoid throughput problems.

[jakobbotsch]

Or maybe the ldr=>ldp peephole could look back more than one instruction? The trick would be to avoid throughput problems.

We also need some interference checking on instrDescs to do that (ensuring the register hasn't changed values and the def can be moved back)... we would also need to be able to change the past ldr instrDesc which I think we had some trouble with (current approach is to remove it and reinsert the ldp, I believe).

[jakobbotsch]

Duplicate of #64815